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CPU: Implement instruction cache simulation

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Implemented for all execution modes. Disabled by default in the cached
interpreter and recompiler, always enabled in the pure interpreter.
This commit is contained in:
Connor McLaughlin
2020-08-29 22:07:33 +10:00
parent efc00a2d0e
commit 19d6037b99
19 changed files with 449 additions and 75 deletions
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8
src/core/cpu_core.cpp
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@ -80,6 +80,8 @@ void Reset()
g_state.cop0_regs.sr.bits = 0;
g_state.cop0_regs.cause.bits = 0;
ClearICache();
GTE::Reset();
SetPC(RESET_VECTOR);
@ -117,14 +119,17 @@ bool DoState(StateWrapper& sw)
sw.Do(&g_state.load_delay_value);
sw.Do(&g_state.next_load_delay_reg);
sw.Do(&g_state.next_load_delay_value);
sw.Do(&g_state.cache_control);
sw.Do(&g_state.cache_control.bits);
sw.DoBytes(g_state.dcache.data(), g_state.dcache.size());
if (!GTE::DoState(sw))
return false;
if (sw.IsReading())
{
ClearICache();
PGXP::Initialize();
}
return !sw.HasError();
}
@ -1416,7 +1421,6 @@ void InterpretCachedBlock(const CodeBlock& block)
{
// set up the state so we've already fetched the instruction
DebugAssert(g_state.regs.pc == block.GetPC());
g_state.regs.npc = block.GetPC() + 4;
for (const CodeBlockInstruction& cbi : block.instructions)