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https://github.com/WinampDesktop/winamp.git
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CPU: Implement PGXP CPU Mode
This is *very* slow. You don't want to enable it if you don't need it. It is also incompatible with the recompiler and will disable it if the option is enabled.
This commit is contained in:
Connor McLaughlin
@ -15,19 +15,9 @@ Log_SetChannel(CPU::Core);
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namespace CPU {
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/// Sets the PC and flushes the pipeline.
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static void SetPC(u32 new_pc);
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// Updates load delays - call after each instruction
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static void UpdateLoadDelay();
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// Fetches the instruction at m_regs.npc
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static void ExecuteInstruction();
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static void ExecuteCop0Instruction();
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static void ExecuteCop2Instruction();
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static void Branch(u32 target);
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// clears pipeline of load/branch delays
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static void FlushPipeline();
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State g_state;
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@ -139,14 +129,14 @@ bool DoState(StateWrapper& sw)
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return !sw.HasError();
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}
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void SetPC(u32 new_pc)
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ALWAYS_INLINE_RELEASE void SetPC(u32 new_pc)
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{
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DebugAssert(Common::IsAlignedPow2(new_pc, 4));
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g_state.regs.npc = new_pc;
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FlushPipeline();
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}
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void Branch(u32 target)
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ALWAYS_INLINE_RELEASE void Branch(u32 target)
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{
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if (!Common::IsAlignedPow2(target, 4))
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{
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@ -240,7 +230,7 @@ void ClearExternalInterrupt(u8 bit)
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g_state.cop0_regs.cause.Ip &= static_cast<u8>(~(1u << bit));
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}
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void UpdateLoadDelay()
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ALWAYS_INLINE_RELEASE static void UpdateLoadDelay()
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{
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// the old value is needed in case the delay slot instruction overwrites the same register
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if (g_state.load_delay_reg != Reg::count)
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@ -251,7 +241,7 @@ void UpdateLoadDelay()
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g_state.next_load_delay_reg = Reg::count;
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}
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void FlushPipeline()
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ALWAYS_INLINE_RELEASE static void FlushPipeline()
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{
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// loads are flushed
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g_state.next_load_delay_reg = Reg::count;
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@ -275,12 +265,12 @@ void FlushPipeline()
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g_state.current_instruction_was_branch_taken = false;
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}
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ALWAYS_INLINE u32 ReadReg(Reg rs)
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ALWAYS_INLINE static u32 ReadReg(Reg rs)
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{
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return g_state.regs.r[static_cast<u8>(rs)];
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}
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ALWAYS_INLINE void WriteReg(Reg rd, u32 value)
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ALWAYS_INLINE static void WriteReg(Reg rd, u32 value)
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{
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g_state.regs.r[static_cast<u8>(rd)] = value;
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g_state.load_delay_reg = (rd == g_state.load_delay_reg) ? Reg::count : g_state.load_delay_reg;
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@ -289,7 +279,7 @@ ALWAYS_INLINE void WriteReg(Reg rd, u32 value)
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g_state.regs.zero = 0;
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}
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static void WriteRegDelayed(Reg rd, u32 value)
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ALWAYS_INLINE_RELEASE static void WriteRegDelayed(Reg rd, u32 value)
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{
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Assert(g_state.next_load_delay_reg == Reg::count);
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if (rd == Reg::zero)
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@ -304,7 +294,7 @@ static void WriteRegDelayed(Reg rd, u32 value)
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g_state.next_load_delay_value = value;
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}
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static std::optional<u32> ReadCop0Reg(Cop0Reg reg)
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ALWAYS_INLINE_RELEASE static std::optional<u32> ReadCop0Reg(Cop0Reg reg)
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{
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switch (reg)
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{
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@ -347,7 +337,7 @@ static std::optional<u32> ReadCop0Reg(Cop0Reg reg)
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}
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}
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static void WriteCop0Reg(Cop0Reg reg, u32 value)
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ALWAYS_INLINE_RELEASE static void WriteCop0Reg(Cop0Reg reg, u32 value)
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{
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switch (reg)
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{
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@ -431,12 +421,12 @@ static void LogInstruction(u32 bits, u32 pc, Registers* regs)
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WriteToExecutionLog("%08x: %08x %s\n", pc, bits, instr.GetCharArray());
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}
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static constexpr bool AddOverflow(u32 old_value, u32 add_value, u32 new_value)
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ALWAYS_INLINE static constexpr bool AddOverflow(u32 old_value, u32 add_value, u32 new_value)
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{
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return (((new_value ^ old_value) & (new_value ^ add_value)) & UINT32_C(0x80000000)) != 0;
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}
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static constexpr bool SubOverflow(u32 old_value, u32 sub_value, u32 new_value)
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ALWAYS_INLINE static constexpr bool SubOverflow(u32 old_value, u32 sub_value, u32 new_value)
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{
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return (((new_value ^ old_value) & (old_value ^ sub_value)) & UINT32_C(0x80000000)) != 0;
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}
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@ -467,53 +457,8 @@ void DisassembleAndPrint(u32 addr, u32 instructions_before /* = 0 */, u32 instru
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}
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}
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void Execute()
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{
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g_state.frame_done = false;
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while (!g_state.frame_done)
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{
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TimingEvents::UpdateCPUDowncount();
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while (g_state.pending_ticks <= g_state.downcount)
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{
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if (HasPendingInterrupt())
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DispatchInterrupt();
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g_state.pending_ticks++;
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// now executing the instruction we previously fetched
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g_state.current_instruction.bits = g_state.next_instruction.bits;
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g_state.current_instruction_pc = g_state.regs.pc;
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g_state.current_instruction_in_branch_delay_slot = g_state.next_instruction_is_branch_delay_slot;
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g_state.current_instruction_was_branch_taken = g_state.branch_was_taken;
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g_state.next_instruction_is_branch_delay_slot = false;
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g_state.branch_was_taken = false;
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g_state.exception_raised = false;
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// fetch the next instruction
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if (!FetchInstruction())
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continue;
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#if 0 // GTE flag test debugging
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if (g_state.m_current_instruction_pc == 0x8002cdf4)
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{
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if (g_state.m_regs.v1 != g_state.m_regs.v0)
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printf("Got %08X Expected? %08X\n", g_state.m_regs.v1, g_state.m_regs.v0);
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}
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#endif
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// execute the instruction we previously fetched
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ExecuteInstruction();
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// next load delay
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UpdateLoadDelay();
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}
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TimingEvents::RunEvents();
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}
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}
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void ExecuteInstruction()
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template<PGXPMode pgxp_mode>
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ALWAYS_INLINE_RELEASE static void ExecuteInstruction()
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{
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const Instruction inst = g_state.current_instruction;
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@ -525,14 +470,6 @@ void ExecuteInstruction()
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}
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#endif
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#if 0
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if (g_state.m_current_instruction_pc == 0x8002bf50)
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{
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TRACE_EXECUTION = true;
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__debugbreak();
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}
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#endif
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#ifdef _DEBUG
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if (TRACE_EXECUTION)
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PrintInstruction(inst.bits, g_state.current_instruction_pc, &g_state.regs);
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@ -549,6 +486,9 @@ void ExecuteInstruction()
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case InstructionFunct::sll:
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{
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const u32 new_value = ReadReg(inst.r.rt) << inst.r.shamt;
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if constexpr (pgxp_mode >= PGXPMode::CPU)
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PGXP::CPU_SLL(inst.bits, new_value, ReadReg(inst.r.rt));
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WriteReg(inst.r.rd, new_value);
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}
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break;
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@ -556,6 +496,9 @@ void ExecuteInstruction()
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case InstructionFunct::srl:
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{
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const u32 new_value = ReadReg(inst.r.rt) >> inst.r.shamt;
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if constexpr (pgxp_mode >= PGXPMode::CPU)
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PGXP::CPU_SRL(inst.bits, new_value, ReadReg(inst.r.rt));
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WriteReg(inst.r.rd, new_value);
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}
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break;
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@ -563,6 +506,9 @@ void ExecuteInstruction()
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case InstructionFunct::sra:
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{
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const u32 new_value = static_cast<u32>(static_cast<s32>(ReadReg(inst.r.rt)) >> inst.r.shamt);
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if constexpr (pgxp_mode >= PGXPMode::CPU)
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PGXP::CPU_SRA(inst.bits, new_value, ReadReg(inst.r.rt));
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WriteReg(inst.r.rd, new_value);
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}
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break;
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@ -571,6 +517,9 @@ void ExecuteInstruction()
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{
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const u32 shift_amount = ReadReg(inst.r.rs) & UINT32_C(0x1F);
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const u32 new_value = ReadReg(inst.r.rt) << shift_amount;
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if constexpr (pgxp_mode >= PGXPMode::CPU)
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PGXP::CPU_SLLV(inst.bits, new_value, ReadReg(inst.r.rt), shift_amount);
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WriteReg(inst.r.rd, new_value);
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}
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break;
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@ -579,6 +528,9 @@ void ExecuteInstruction()
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{
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const u32 shift_amount = ReadReg(inst.r.rs) & UINT32_C(0x1F);
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const u32 new_value = ReadReg(inst.r.rt) >> shift_amount;
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if constexpr (pgxp_mode >= PGXPMode::CPU)
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PGXP::CPU_SRLV(inst.bits, new_value, ReadReg(inst.r.rt), shift_amount);
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WriteReg(inst.r.rd, new_value);
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}
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break;
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@ -587,6 +539,9 @@ void ExecuteInstruction()
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{
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const u32 shift_amount = ReadReg(inst.r.rs) & UINT32_C(0x1F);
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const u32 new_value = static_cast<u32>(static_cast<s32>(ReadReg(inst.r.rt)) >> shift_amount);
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if constexpr (pgxp_mode >= PGXPMode::CPU)
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PGXP::CPU_SRAV(inst.bits, new_value, ReadReg(inst.r.rt), shift_amount);
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WriteReg(inst.r.rd, new_value);
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}
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break;
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@ -594,6 +549,9 @@ void ExecuteInstruction()
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case InstructionFunct::and_:
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{
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const u32 new_value = ReadReg(inst.r.rs) & ReadReg(inst.r.rt);
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if constexpr (pgxp_mode >= PGXPMode::CPU)
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PGXP::CPU_AND(inst.bits, new_value, ReadReg(inst.r.rs), ReadReg(inst.r.rt));
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WriteReg(inst.r.rd, new_value);
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}
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break;
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@ -601,6 +559,9 @@ void ExecuteInstruction()
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case InstructionFunct::or_:
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{
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const u32 new_value = ReadReg(inst.r.rs) | ReadReg(inst.r.rt);
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if constexpr (pgxp_mode >= PGXPMode::CPU)
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PGXP::CPU_OR(inst.bits, new_value, ReadReg(inst.r.rs), ReadReg(inst.r.rt));
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WriteReg(inst.r.rd, new_value);
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}
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break;
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@ -608,6 +569,9 @@ void ExecuteInstruction()
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case InstructionFunct::xor_:
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{
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const u32 new_value = ReadReg(inst.r.rs) ^ ReadReg(inst.r.rt);
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if constexpr (pgxp_mode >= PGXPMode::CPU)
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PGXP::CPU_XOR(inst.bits, new_value, ReadReg(inst.r.rs), ReadReg(inst.r.rt));
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WriteReg(inst.r.rd, new_value);
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}
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break;
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@ -615,6 +579,9 @@ void ExecuteInstruction()
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case InstructionFunct::nor:
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{
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const u32 new_value = ~(ReadReg(inst.r.rs) | ReadReg(inst.r.rt));
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if constexpr (pgxp_mode >= PGXPMode::CPU)
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PGXP::CPU_NOR(inst.bits, new_value, ReadReg(inst.r.rs), ReadReg(inst.r.rt));
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WriteReg(inst.r.rd, new_value);
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}
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break;
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@ -630,6 +597,9 @@ void ExecuteInstruction()
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return;
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}
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if constexpr (pgxp_mode == PGXPMode::CPU)
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PGXP::CPU_ADD(inst.bits, new_value, ReadReg(inst.r.rs), ReadReg(inst.r.rt));
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WriteReg(inst.r.rd, new_value);
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}
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break;
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@ -637,6 +607,9 @@ void ExecuteInstruction()
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case InstructionFunct::addu:
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{
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const u32 new_value = ReadReg(inst.r.rs) + ReadReg(inst.r.rt);
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if constexpr (pgxp_mode >= PGXPMode::CPU)
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PGXP::CPU_ADDU(inst.bits, new_value, ReadReg(inst.r.rs), ReadReg(inst.r.rt));
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WriteReg(inst.r.rd, new_value);
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}
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break;
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@ -652,6 +625,9 @@ void ExecuteInstruction()
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return;
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}
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if constexpr (pgxp_mode >= PGXPMode::CPU)
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PGXP::CPU_SUB(inst.bits, new_value, ReadReg(inst.r.rs), ReadReg(inst.r.rt));
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WriteReg(inst.r.rd, new_value);
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}
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break;
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@ -659,6 +635,9 @@ void ExecuteInstruction()
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case InstructionFunct::subu:
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{
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const u32 new_value = ReadReg(inst.r.rs) - ReadReg(inst.r.rt);
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if constexpr (pgxp_mode >= PGXPMode::CPU)
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PGXP::CPU_SUBU(inst.bits, new_value, ReadReg(inst.r.rs), ReadReg(inst.r.rt));
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WriteReg(inst.r.rd, new_value);
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}
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break;
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@ -666,6 +645,9 @@ void ExecuteInstruction()
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case InstructionFunct::slt:
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{
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const u32 result = BoolToUInt32(static_cast<s32>(ReadReg(inst.r.rs)) < static_cast<s32>(ReadReg(inst.r.rt)));
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if constexpr (pgxp_mode >= PGXPMode::CPU)
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PGXP::CPU_SLT(inst.bits, result, ReadReg(inst.r.rs), ReadReg(inst.r.rt));
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WriteReg(inst.r.rd, result);
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}
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break;
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@ -673,12 +655,18 @@ void ExecuteInstruction()
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case InstructionFunct::sltu:
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{
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const u32 result = BoolToUInt32(ReadReg(inst.r.rs) < ReadReg(inst.r.rt));
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if constexpr (pgxp_mode >= PGXPMode::CPU)
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PGXP::CPU_SLTU(inst.bits, result, ReadReg(inst.r.rs), ReadReg(inst.r.rt));
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WriteReg(inst.r.rd, result);
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}
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break;
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case InstructionFunct::mfhi:
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{
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if constexpr (pgxp_mode >= PGXPMode::CPU)
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PGXP::CPU_MFHI(inst.bits, ReadReg(inst.r.rd), g_state.regs.hi);
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WriteReg(inst.r.rd, g_state.regs.hi);
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}
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break;
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@ -686,12 +674,18 @@ void ExecuteInstruction()
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case InstructionFunct::mthi:
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{
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const u32 value = ReadReg(inst.r.rs);
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if constexpr (pgxp_mode >= PGXPMode::CPU)
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PGXP::CPU_MTHI(inst.bits, g_state.regs.hi, value);
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g_state.regs.hi = value;
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}
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break;
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case InstructionFunct::mflo:
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{
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if constexpr (pgxp_mode >= PGXPMode::CPU)
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PGXP::CPU_MFLO(inst.bits, ReadReg(inst.r.rd), g_state.regs.lo);
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WriteReg(inst.r.rd, g_state.regs.lo);
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}
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break;
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@ -699,6 +693,9 @@ void ExecuteInstruction()
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case InstructionFunct::mtlo:
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{
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const u32 value = ReadReg(inst.r.rs);
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if constexpr (pgxp_mode == PGXPMode::CPU)
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PGXP::CPU_MTLO(inst.bits, g_state.regs.lo, value);
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g_state.regs.lo = value;
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}
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break;
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@ -709,8 +706,12 @@ void ExecuteInstruction()
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const u32 rhs = ReadReg(inst.r.rt);
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const u64 result =
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static_cast<u64>(static_cast<s64>(SignExtend64(lhs)) * static_cast<s64>(SignExtend64(rhs)));
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g_state.regs.hi = Truncate32(result >> 32);
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g_state.regs.lo = Truncate32(result);
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if constexpr (pgxp_mode >= PGXPMode::CPU)
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PGXP::CPU_MULT(inst.bits, g_state.regs.hi, g_state.regs.lo, lhs, rhs);
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}
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break;
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@ -719,6 +720,10 @@ void ExecuteInstruction()
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const u32 lhs = ReadReg(inst.r.rs);
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const u32 rhs = ReadReg(inst.r.rt);
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const u64 result = ZeroExtend64(lhs) * ZeroExtend64(rhs);
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if constexpr (pgxp_mode >= PGXPMode::CPU)
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PGXP::CPU_MULTU(inst.bits, g_state.regs.hi, g_state.regs.lo, lhs, rhs);
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g_state.regs.hi = Truncate32(result >> 32);
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g_state.regs.lo = Truncate32(result);
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}
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@ -746,6 +751,9 @@ void ExecuteInstruction()
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g_state.regs.lo = static_cast<u32>(num / denom);
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g_state.regs.hi = static_cast<u32>(num % denom);
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}
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if constexpr (pgxp_mode >= PGXPMode::CPU)
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PGXP::CPU_DIV(inst.bits, g_state.regs.hi, g_state.regs.lo, num, denom);
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}
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break;
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@ -765,6 +773,9 @@ void ExecuteInstruction()
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g_state.regs.lo = num / denom;
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g_state.regs.hi = num % denom;
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}
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if constexpr (pgxp_mode >= PGXPMode::CPU)
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PGXP::CPU_DIVU(inst.bits, g_state.regs.hi, g_state.regs.lo, num, denom);
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}
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break;
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@ -808,25 +819,44 @@ void ExecuteInstruction()
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case InstructionOp::lui:
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{
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WriteReg(inst.i.rt, inst.i.imm_zext32() << 16);
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const u32 value = inst.i.imm_zext32() << 16;
|
||||
WriteReg(inst.i.rt, value);
|
||||
|
||||
if constexpr (pgxp_mode >= PGXPMode::CPU)
|
||||
PGXP::CPU_LUI(inst.bits, value);
|
||||
}
|
||||
break;
|
||||
|
||||
case InstructionOp::andi:
|
||||
{
|
||||
WriteReg(inst.i.rt, ReadReg(inst.i.rs) & inst.i.imm_zext32());
|
||||
const u32 new_value = ReadReg(inst.i.rs) & inst.i.imm_zext32();
|
||||
|
||||
if constexpr (pgxp_mode >= PGXPMode::CPU)
|
||||
PGXP::CPU_ANDI(inst.bits, new_value, ReadReg(inst.i.rs));
|
||||
|
||||
WriteReg(inst.i.rt, new_value);
|
||||
}
|
||||
break;
|
||||
|
||||
case InstructionOp::ori:
|
||||
{
|
||||
WriteReg(inst.i.rt, ReadReg(inst.i.rs) | inst.i.imm_zext32());
|
||||
const u32 new_value = ReadReg(inst.i.rs) | inst.i.imm_zext32();
|
||||
|
||||
if constexpr (pgxp_mode >= PGXPMode::CPU)
|
||||
PGXP::CPU_ORI(inst.bits, new_value, ReadReg(inst.i.rs));
|
||||
|
||||
WriteReg(inst.i.rt, new_value);
|
||||
}
|
||||
break;
|
||||
|
||||
case InstructionOp::xori:
|
||||
{
|
||||
WriteReg(inst.i.rt, ReadReg(inst.i.rs) ^ inst.i.imm_zext32());
|
||||
const u32 new_value = ReadReg(inst.i.rs) ^ inst.i.imm_zext32();
|
||||
|
||||
if constexpr (pgxp_mode >= PGXPMode::CPU)
|
||||
PGXP::CPU_XORI(inst.bits, new_value, ReadReg(inst.i.rs));
|
||||
|
||||
WriteReg(inst.i.rt, new_value);
|
||||
}
|
||||
break;
|
||||
|
||||
@ -841,19 +871,31 @@ void ExecuteInstruction()
|
||||
return;
|
||||
}
|
||||
|
||||
if constexpr (pgxp_mode >= PGXPMode::CPU)
|
||||
PGXP::CPU_ANDI(inst.bits, new_value, ReadReg(inst.i.rs));
|
||||
|
||||
WriteReg(inst.i.rt, new_value);
|
||||
}
|
||||
break;
|
||||
|
||||
case InstructionOp::addiu:
|
||||
{
|
||||
WriteReg(inst.i.rt, ReadReg(inst.i.rs) + inst.i.imm_sext32());
|
||||
const u32 new_value = ReadReg(inst.i.rs) + inst.i.imm_sext32();
|
||||
|
||||
if constexpr (pgxp_mode >= PGXPMode::CPU)
|
||||
PGXP::CPU_ADDIU(inst.bits, new_value, ReadReg(inst.i.rs));
|
||||
|
||||
WriteReg(inst.i.rt, new_value);
|
||||
}
|
||||
break;
|
||||
|
||||
case InstructionOp::slti:
|
||||
{
|
||||
const u32 result = BoolToUInt32(static_cast<s32>(ReadReg(inst.i.rs)) < static_cast<s32>(inst.i.imm_sext32()));
|
||||
|
||||
if constexpr (pgxp_mode >= PGXPMode::CPU)
|
||||
PGXP::CPU_SLTI(inst.bits, result, ReadReg(inst.i.rs));
|
||||
|
||||
WriteReg(inst.i.rt, result);
|
||||
}
|
||||
break;
|
||||
@ -861,6 +903,10 @@ void ExecuteInstruction()
|
||||
case InstructionOp::sltiu:
|
||||
{
|
||||
const u32 result = BoolToUInt32(ReadReg(inst.i.rs) < inst.i.imm_sext32());
|
||||
|
||||
if constexpr (pgxp_mode >= PGXPMode::CPU)
|
||||
PGXP::CPU_SLTIU(inst.bits, result, ReadReg(inst.i.rs));
|
||||
|
||||
WriteReg(inst.i.rt, result);
|
||||
}
|
||||
break;
|
||||
@ -876,7 +922,7 @@ void ExecuteInstruction()
|
||||
|
||||
WriteRegDelayed(inst.i.rt, sxvalue);
|
||||
|
||||
if (g_settings.gpu_pgxp_enable)
|
||||
if constexpr (pgxp_mode >= PGXPMode::Memory)
|
||||
PGXP::CPU_LBx(inst.bits, sxvalue, addr);
|
||||
}
|
||||
break;
|
||||
@ -891,7 +937,7 @@ void ExecuteInstruction()
|
||||
const u32 sxvalue = SignExtend32(value);
|
||||
WriteRegDelayed(inst.i.rt, sxvalue);
|
||||
|
||||
if (g_settings.gpu_pgxp_enable)
|
||||
if constexpr (pgxp_mode >= PGXPMode::Memory)
|
||||
PGXP::CPU_LHx(inst.bits, sxvalue, addr);
|
||||
}
|
||||
break;
|
||||
@ -905,7 +951,7 @@ void ExecuteInstruction()
|
||||
|
||||
WriteRegDelayed(inst.i.rt, value);
|
||||
|
||||
if (g_settings.gpu_pgxp_enable)
|
||||
if constexpr (pgxp_mode >= PGXPMode::Memory)
|
||||
PGXP::CPU_LW(inst.bits, value, addr);
|
||||
}
|
||||
break;
|
||||
@ -920,7 +966,7 @@ void ExecuteInstruction()
|
||||
const u32 zxvalue = ZeroExtend32(value);
|
||||
WriteRegDelayed(inst.i.rt, zxvalue);
|
||||
|
||||
if (g_settings.gpu_pgxp_enable)
|
||||
if constexpr (pgxp_mode >= PGXPMode::Memory)
|
||||
PGXP::CPU_LBx(inst.bits, zxvalue, addr);
|
||||
}
|
||||
break;
|
||||
@ -935,7 +981,7 @@ void ExecuteInstruction()
|
||||
const u32 zxvalue = ZeroExtend32(value);
|
||||
WriteRegDelayed(inst.i.rt, zxvalue);
|
||||
|
||||
if (g_settings.gpu_pgxp_enable)
|
||||
if constexpr (pgxp_mode >= PGXPMode::Memory)
|
||||
PGXP::CPU_LHx(inst.bits, zxvalue, addr);
|
||||
}
|
||||
break;
|
||||
@ -966,7 +1012,7 @@ void ExecuteInstruction()
|
||||
|
||||
WriteRegDelayed(inst.i.rt, new_value);
|
||||
|
||||
if (g_settings.gpu_pgxp_enable)
|
||||
if constexpr (pgxp_mode >= PGXPMode::Memory)
|
||||
PGXP::CPU_LW(inst.bits, new_value, addr);
|
||||
}
|
||||
break;
|
||||
@ -977,7 +1023,7 @@ void ExecuteInstruction()
|
||||
const u8 value = Truncate8(ReadReg(inst.i.rt));
|
||||
WriteMemoryByte(addr, value);
|
||||
|
||||
if (g_settings.gpu_pgxp_enable)
|
||||
if constexpr (pgxp_mode >= PGXPMode::Memory)
|
||||
PGXP::CPU_SB(inst.bits, value, addr);
|
||||
}
|
||||
break;
|
||||
@ -988,7 +1034,7 @@ void ExecuteInstruction()
|
||||
const u16 value = Truncate16(ReadReg(inst.i.rt));
|
||||
WriteMemoryHalfWord(addr, value);
|
||||
|
||||
if (g_settings.gpu_pgxp_enable)
|
||||
if constexpr (pgxp_mode >= PGXPMode::Memory)
|
||||
PGXP::CPU_SH(inst.bits, value, addr);
|
||||
}
|
||||
break;
|
||||
@ -999,7 +1045,7 @@ void ExecuteInstruction()
|
||||
const u32 value = ReadReg(inst.i.rt);
|
||||
WriteMemoryWord(addr, value);
|
||||
|
||||
if (g_settings.gpu_pgxp_enable)
|
||||
if constexpr (pgxp_mode >= PGXPMode::Memory)
|
||||
PGXP::CPU_SW(inst.bits, value, addr);
|
||||
}
|
||||
break;
|
||||
@ -1029,7 +1075,7 @@ void ExecuteInstruction()
|
||||
|
||||
WriteMemoryWord(aligned_addr, new_value);
|
||||
|
||||
if (g_settings.gpu_pgxp_enable)
|
||||
if constexpr (pgxp_mode >= PGXPMode::Memory)
|
||||
PGXP::CPU_SW(inst.bits, new_value, addr);
|
||||
}
|
||||
break;
|
||||
@ -1114,7 +1160,58 @@ void ExecuteInstruction()
|
||||
return;
|
||||
}
|
||||
|
||||
ExecuteCop0Instruction();
|
||||
if (inst.cop.IsCommonInstruction())
|
||||
{
|
||||
switch (inst.cop.CommonOp())
|
||||
{
|
||||
case CopCommonInstruction::mfcn:
|
||||
{
|
||||
const std::optional<u32> value = ReadCop0Reg(static_cast<Cop0Reg>(inst.r.rd.GetValue()));
|
||||
|
||||
if constexpr (pgxp_mode == PGXPMode::CPU)
|
||||
PGXP::CPU_MFC0(inst.bits, value.value_or(0), ReadReg(inst.i.rs));
|
||||
|
||||
if (value)
|
||||
WriteRegDelayed(inst.r.rt, value.value());
|
||||
else
|
||||
RaiseException(Exception::RI);
|
||||
}
|
||||
break;
|
||||
|
||||
case CopCommonInstruction::mtcn:
|
||||
{
|
||||
WriteCop0Reg(static_cast<Cop0Reg>(inst.r.rd.GetValue()), ReadReg(inst.r.rt));
|
||||
|
||||
if constexpr (pgxp_mode == PGXPMode::CPU)
|
||||
{
|
||||
PGXP::CPU_MTC0(inst.bits, ReadCop0Reg(static_cast<Cop0Reg>(inst.r.rd.GetValue())).value_or(0),
|
||||
ReadReg(inst.i.rs));
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
Panic("Missing implementation");
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
switch (inst.cop.Cop0Op())
|
||||
{
|
||||
case Cop0Instruction::rfe:
|
||||
{
|
||||
// restore mode
|
||||
g_state.cop0_regs.sr.mode_bits =
|
||||
(g_state.cop0_regs.sr.mode_bits & UINT32_C(0b110000)) | (g_state.cop0_regs.sr.mode_bits >> 2);
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
Panic("Missing implementation");
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
@ -1127,7 +1224,61 @@ void ExecuteInstruction()
|
||||
return;
|
||||
}
|
||||
|
||||
ExecuteCop2Instruction();
|
||||
if (inst.cop.IsCommonInstruction())
|
||||
{
|
||||
// TODO: Combine with cop0.
|
||||
switch (inst.cop.CommonOp())
|
||||
{
|
||||
case CopCommonInstruction::cfcn:
|
||||
{
|
||||
const u32 value = GTE::ReadRegister(static_cast<u32>(inst.r.rd.GetValue()) + 32);
|
||||
WriteRegDelayed(inst.r.rt, value);
|
||||
|
||||
if constexpr (pgxp_mode >= PGXPMode::Memory)
|
||||
PGXP::CPU_CFC2(inst.bits, value, value);
|
||||
}
|
||||
break;
|
||||
|
||||
case CopCommonInstruction::ctcn:
|
||||
{
|
||||
const u32 value = ReadReg(inst.r.rt);
|
||||
GTE::WriteRegister(static_cast<u32>(inst.r.rd.GetValue()) + 32, value);
|
||||
|
||||
if constexpr (pgxp_mode >= PGXPMode::Memory)
|
||||
PGXP::CPU_CTC2(inst.bits, value, value);
|
||||
}
|
||||
break;
|
||||
|
||||
case CopCommonInstruction::mfcn:
|
||||
{
|
||||
const u32 value = GTE::ReadRegister(static_cast<u32>(inst.r.rd.GetValue()));
|
||||
WriteRegDelayed(inst.r.rt, value);
|
||||
|
||||
if constexpr (pgxp_mode >= PGXPMode::Memory)
|
||||
PGXP::CPU_MFC2(inst.bits, value, value);
|
||||
}
|
||||
break;
|
||||
|
||||
case CopCommonInstruction::mtcn:
|
||||
{
|
||||
const u32 value = ReadReg(inst.r.rt);
|
||||
GTE::WriteRegister(static_cast<u32>(inst.r.rd.GetValue()), value);
|
||||
|
||||
if constexpr (pgxp_mode >= PGXPMode::Memory)
|
||||
PGXP::CPU_MTC2(inst.bits, value, value);
|
||||
}
|
||||
break;
|
||||
|
||||
case CopCommonInstruction::bcnc:
|
||||
default:
|
||||
Panic("Missing implementation");
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
GTE::ExecuteInstruction(inst.bits);
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
@ -1147,7 +1298,7 @@ void ExecuteInstruction()
|
||||
|
||||
GTE::WriteRegister(ZeroExtend32(static_cast<u8>(inst.i.rt.GetValue())), value);
|
||||
|
||||
if (g_settings.gpu_pgxp_enable)
|
||||
if constexpr (pgxp_mode >= PGXPMode::Memory)
|
||||
PGXP::CPU_LWC2(inst.bits, value, addr);
|
||||
}
|
||||
break;
|
||||
@ -1165,12 +1316,12 @@ void ExecuteInstruction()
|
||||
const u32 value = GTE::ReadRegister(ZeroExtend32(static_cast<u8>(inst.i.rt.GetValue())));
|
||||
WriteMemoryWord(addr, value);
|
||||
|
||||
if (g_settings.gpu_pgxp_enable)
|
||||
if constexpr (pgxp_mode >= PGXPMode::Memory)
|
||||
PGXP::CPU_SWC2(inst.bits, value, addr);
|
||||
}
|
||||
break;
|
||||
|
||||
// swc0/lwc0/cop1/cop3 are essentially no-ops
|
||||
// swc0/lwc0/cop1/cop3 are essentially no-ops
|
||||
case InstructionOp::cop1:
|
||||
case InstructionOp::cop3:
|
||||
case InstructionOp::lwc0:
|
||||
@ -1183,7 +1334,7 @@ void ExecuteInstruction()
|
||||
}
|
||||
break;
|
||||
|
||||
// everything else is reserved/invalid
|
||||
// everything else is reserved/invalid
|
||||
default:
|
||||
{
|
||||
RaiseException(Exception::RI);
|
||||
@ -1192,117 +1343,71 @@ void ExecuteInstruction()
|
||||
}
|
||||
}
|
||||
|
||||
void ExecuteCop0Instruction()
|
||||
template<PGXPMode pgxp_mode>
|
||||
static void ExecuteImpl()
|
||||
{
|
||||
const Instruction inst = g_state.current_instruction;
|
||||
|
||||
if (inst.cop.IsCommonInstruction())
|
||||
g_state.frame_done = false;
|
||||
while (!g_state.frame_done)
|
||||
{
|
||||
switch (inst.cop.CommonOp())
|
||||
TimingEvents::UpdateCPUDowncount();
|
||||
|
||||
while (g_state.pending_ticks <= g_state.downcount)
|
||||
{
|
||||
case CopCommonInstruction::mfcn:
|
||||
{
|
||||
const std::optional<u32> value = ReadCop0Reg(static_cast<Cop0Reg>(inst.r.rd.GetValue()));
|
||||
if (value)
|
||||
WriteRegDelayed(inst.r.rt, value.value());
|
||||
else
|
||||
RaiseException(Exception::RI);
|
||||
}
|
||||
break;
|
||||
if (HasPendingInterrupt())
|
||||
DispatchInterrupt();
|
||||
|
||||
case CopCommonInstruction::mtcn:
|
||||
{
|
||||
WriteCop0Reg(static_cast<Cop0Reg>(inst.r.rd.GetValue()), ReadReg(inst.r.rt));
|
||||
}
|
||||
break;
|
||||
g_state.pending_ticks++;
|
||||
|
||||
default:
|
||||
Panic("Missing implementation");
|
||||
break;
|
||||
// now executing the instruction we previously fetched
|
||||
g_state.current_instruction.bits = g_state.next_instruction.bits;
|
||||
g_state.current_instruction_pc = g_state.regs.pc;
|
||||
g_state.current_instruction_in_branch_delay_slot = g_state.next_instruction_is_branch_delay_slot;
|
||||
g_state.current_instruction_was_branch_taken = g_state.branch_was_taken;
|
||||
g_state.next_instruction_is_branch_delay_slot = false;
|
||||
g_state.branch_was_taken = false;
|
||||
g_state.exception_raised = false;
|
||||
|
||||
// fetch the next instruction
|
||||
if (!FetchInstruction())
|
||||
continue;
|
||||
|
||||
#if 0 // GTE flag test debugging
|
||||
if (g_state.m_current_instruction_pc == 0x8002cdf4)
|
||||
{
|
||||
if (g_state.m_regs.v1 != g_state.m_regs.v0)
|
||||
printf("Got %08X Expected? %08X\n", g_state.m_regs.v1, g_state.m_regs.v0);
|
||||
}
|
||||
#endif
|
||||
|
||||
// execute the instruction we previously fetched
|
||||
ExecuteInstruction<pgxp_mode>();
|
||||
|
||||
// next load delay
|
||||
UpdateLoadDelay();
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
switch (inst.cop.Cop0Op())
|
||||
{
|
||||
case Cop0Instruction::rfe:
|
||||
{
|
||||
// restore mode
|
||||
g_state.cop0_regs.sr.mode_bits =
|
||||
(g_state.cop0_regs.sr.mode_bits & UINT32_C(0b110000)) | (g_state.cop0_regs.sr.mode_bits >> 2);
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
Panic("Missing implementation");
|
||||
break;
|
||||
}
|
||||
TimingEvents::RunEvents();
|
||||
}
|
||||
}
|
||||
|
||||
void ExecuteCop2Instruction()
|
||||
void Execute()
|
||||
{
|
||||
const Instruction inst = g_state.current_instruction;
|
||||
|
||||
if (inst.cop.IsCommonInstruction())
|
||||
if (g_settings.gpu_pgxp_enable)
|
||||
{
|
||||
// TODO: Combine with cop0.
|
||||
switch (inst.cop.CommonOp())
|
||||
{
|
||||
case CopCommonInstruction::cfcn:
|
||||
{
|
||||
const u32 value = GTE::ReadRegister(static_cast<u32>(inst.r.rd.GetValue()) + 32);
|
||||
WriteRegDelayed(inst.r.rt, value);
|
||||
|
||||
if (g_settings.gpu_pgxp_enable)
|
||||
PGXP::CPU_CFC2(inst.bits, value, value);
|
||||
}
|
||||
break;
|
||||
|
||||
case CopCommonInstruction::ctcn:
|
||||
{
|
||||
const u32 value = ReadReg(inst.r.rt);
|
||||
GTE::WriteRegister(static_cast<u32>(inst.r.rd.GetValue()) + 32, value);
|
||||
|
||||
if (g_settings.gpu_pgxp_enable)
|
||||
PGXP::CPU_CTC2(inst.bits, value, value);
|
||||
}
|
||||
break;
|
||||
|
||||
case CopCommonInstruction::mfcn:
|
||||
{
|
||||
const u32 value = GTE::ReadRegister(static_cast<u32>(inst.r.rd.GetValue()));
|
||||
WriteRegDelayed(inst.r.rt, value);
|
||||
|
||||
if (g_settings.gpu_pgxp_enable)
|
||||
PGXP::CPU_MFC2(inst.bits, value, value);
|
||||
}
|
||||
break;
|
||||
|
||||
case CopCommonInstruction::mtcn:
|
||||
{
|
||||
const u32 value = ReadReg(inst.r.rt);
|
||||
GTE::WriteRegister(static_cast<u32>(inst.r.rd.GetValue()), value);
|
||||
|
||||
if (g_settings.gpu_pgxp_enable)
|
||||
PGXP::CPU_MTC2(inst.bits, value, value);
|
||||
}
|
||||
break;
|
||||
|
||||
case CopCommonInstruction::bcnc:
|
||||
default:
|
||||
Panic("Missing implementation");
|
||||
break;
|
||||
}
|
||||
if (g_settings.gpu_pgxp_cpu)
|
||||
ExecuteImpl<PGXPMode::CPU>();
|
||||
else
|
||||
ExecuteImpl<PGXPMode::Memory>();
|
||||
}
|
||||
else
|
||||
{
|
||||
GTE::ExecuteInstruction(inst.bits);
|
||||
ExecuteImpl<PGXPMode::Disabled>();
|
||||
}
|
||||
}
|
||||
|
||||
namespace CodeCache {
|
||||
|
||||
template<PGXPMode pgxp_mode>
|
||||
void InterpretCachedBlock(const CodeBlock& block)
|
||||
{
|
||||
// set up the state so we've already fetched the instruction
|
||||
@ -1327,7 +1432,7 @@ void InterpretCachedBlock(const CodeBlock& block)
|
||||
g_state.regs.npc += 4;
|
||||
|
||||
// execute the instruction we previously fetched
|
||||
ExecuteInstruction();
|
||||
ExecuteInstruction<pgxp_mode>();
|
||||
|
||||
// next load delay
|
||||
UpdateLoadDelay();
|
||||
@ -1340,6 +1445,10 @@ void InterpretCachedBlock(const CodeBlock& block)
|
||||
g_state.next_instruction_is_branch_delay_slot = false;
|
||||
}
|
||||
|
||||
template void InterpretCachedBlock<PGXPMode::Disabled>(const CodeBlock& block);
|
||||
template void InterpretCachedBlock<PGXPMode::Memory>(const CodeBlock& block);
|
||||
template void InterpretCachedBlock<PGXPMode::CPU>(const CodeBlock& block);
|
||||
|
||||
void InterpretUncachedBlock()
|
||||
{
|
||||
Panic("Fixme with regards to re-fetching PC");
|
||||
@ -1365,7 +1474,7 @@ void InterpretUncachedBlock()
|
||||
break;
|
||||
|
||||
// execute the instruction we previously fetched
|
||||
ExecuteInstruction();
|
||||
ExecuteInstruction<PGXPMode::Disabled>();
|
||||
|
||||
// next load delay
|
||||
UpdateLoadDelay();
|
||||
@ -1387,7 +1496,13 @@ namespace Recompiler::Thunks {
|
||||
|
||||
bool InterpretInstruction()
|
||||
{
|
||||
ExecuteInstruction();
|
||||
ExecuteInstruction<PGXPMode::Disabled>();
|
||||
return g_state.exception_raised;
|
||||
}
|
||||
|
||||
bool InterpretInstructionPGXP()
|
||||
{
|
||||
ExecuteInstruction<PGXPMode::Memory>();
|
||||
return g_state.exception_raised;
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user