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CPU/Recompiler: Implement lb/lbu/lh/lhu/lw/sb/sh/sw instructions
Currently not passing CPU tests when combined with lwl/lwr.
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@ -365,7 +365,7 @@ void Core::FlushPipeline()
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m_regs.r[static_cast<u8>(m_load_delay_reg)] = m_load_delay_value;
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m_load_delay_reg = Reg::count;
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}
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// not in a branch delay slot
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m_branch_was_taken = false;
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m_next_instruction_is_branch_delay_slot = false;
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