diff --git a/src/pse/cpu_core.cpp b/src/pse/cpu_core.cpp
index 3fcc49a72..c08be4641 100644
--- a/src/pse/cpu_core.cpp
+++ b/src/pse/cpu_core.cpp
@@ -251,6 +251,11 @@ void Core::ClearExternalInterrupt(u8 bit)
 
 bool Core::DispatchInterrupts()
 {
+  // If the instruction we're about to execute is a GTE instruction, delay dispatching the interrupt until the next
+  // instruction. For some reason, if we don't do this, we end up with incorrectly sorted polygons and flickering..
+  if (m_next_instruction.IsCop2Instruction())
+    return false;
+
   // const bool do_interrupt = m_cop0_regs.sr.IEc && ((m_cop0_regs.cause.Ip & m_cop0_regs.sr.Im) != 0);
   const bool do_interrupt =
     m_cop0_regs.sr.IEc && (((m_cop0_regs.cause.bits & m_cop0_regs.sr.bits) & (UINT32_C(0xFF) << 8)) != 0);
diff --git a/src/pse/cpu_types.h b/src/pse/cpu_types.h
index 65675dced..9f967bc46 100644
--- a/src/pse/cpu_types.h
+++ b/src/pse/cpu_types.h
@@ -182,6 +182,11 @@ union Instruction
 
     Cop0Instruction Cop0Op() const { return static_cast<Cop0Instruction>(bits & UINT32_C(0x3F)); }
   } cop;
+
+  bool IsCop2Instruction() const
+  {
+    return (op == InstructionOp::cop2 || op == InstructionOp::lwc2 || op == InstructionOp::swc2);
+  }
 };
 
 struct Registers