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Bus: Reduce RAM write delay

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This commit is contained in:
Connor McLaughlin
2019-11-27 00:01:47 +10:00
parent b3cf18b593
commit aec01d3890
6 changed files with 64 additions and 41 deletions
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52
src/core/bus.inl
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@ -45,7 +45,7 @@ TickCount Bus::DoRAMAccess(u32 offset, u32& value)
}
// Nocash docs say RAM takes 6 cycles to access.
return RAM_ACCESS_DELAY;
return (type == MemoryAccessType::Read) ? RAM_READ_ACCESS_DELAY : RAM_WRITE_ACCESS_DELAY;
}
template<MemoryAccessType type, MemoryAccessSize size>
@ -92,11 +92,15 @@ TickCount Bus::DispatchAccess(PhysicalMemoryAddress address, u32& value)
else if (address < (EXP1_BASE + EXP1_SIZE))
{
if constexpr (type == MemoryAccessType::Read)
{
value = DoReadEXP1(size, address & EXP1_MASK);
return m_exp1_access_time[static_cast<u32>(size)];
}
else
{
DoWriteEXP1(size, address & EXP1_MASK, value);
return m_exp1_access_time[static_cast<u32>(size)];
return 0;
}
}
else if (address < MEMCTRL_BASE)
{
@ -109,7 +113,7 @@ TickCount Bus::DispatchAccess(PhysicalMemoryAddress address, u32& value)
else
DoWriteMemoryControl(size, address & PAD_MASK, value);
return 1;
return 0;
}
else if (address < (PAD_BASE + PAD_SIZE))
{
@ -118,7 +122,7 @@ TickCount Bus::DispatchAccess(PhysicalMemoryAddress address, u32& value)
else
DoWritePad(size, address & PAD_MASK, value);
return 1;
return 0;
}
else if (address < (SIO_BASE + SIO_SIZE))
{
@ -127,7 +131,7 @@ TickCount Bus::DispatchAccess(PhysicalMemoryAddress address, u32& value)
else
DoWriteSIO(size, address & SIO_MASK, value);
return 1;
return 0;
}
else if (address < (MEMCTRL2_BASE + MEMCTRL2_SIZE))
{
@ -136,7 +140,7 @@ TickCount Bus::DispatchAccess(PhysicalMemoryAddress address, u32& value)
else
DoWriteMemoryControl2(size, address & PAD_MASK, value);
return 1;
return 0;
}
else if (address < (INTERRUPT_CONTROLLER_BASE + INTERRUPT_CONTROLLER_SIZE))
{
@ -145,7 +149,7 @@ TickCount Bus::DispatchAccess(PhysicalMemoryAddress address, u32& value)
else
DoWriteInterruptController(size, address & INTERRUPT_CONTROLLER_MASK, value);
return 1;
return 0;
}
else if (address < (DMA_BASE + DMA_SIZE))
{
@ -154,7 +158,7 @@ TickCount Bus::DispatchAccess(PhysicalMemoryAddress address, u32& value)
else
DoWriteDMA(size, address & DMA_MASK, value);
return 1;
return 0;
}
else if (address < (TIMERS_BASE + TIMERS_SIZE))
{
@ -163,7 +167,7 @@ TickCount Bus::DispatchAccess(PhysicalMemoryAddress address, u32& value)
else
DoWriteTimers(size, address & TIMERS_MASK, value);
return 1;
return 0;
}
else if (address < CDROM_BASE)
{
@ -172,11 +176,15 @@ TickCount Bus::DispatchAccess(PhysicalMemoryAddress address, u32& value)
else if (address < (CDROM_BASE + GPU_SIZE))
{
if constexpr (type == MemoryAccessType::Read)
{
value = DoReadCDROM(size, address & CDROM_MASK);
return m_cdrom_access_time[static_cast<u32>(size)];
}
else
{
DoWriteCDROM(size, address & CDROM_MASK, value);
return m_cdrom_access_time[static_cast<u32>(size)];
return 0;
}
}
else if (address < (GPU_BASE + GPU_SIZE))
{
@ -185,7 +193,7 @@ TickCount Bus::DispatchAccess(PhysicalMemoryAddress address, u32& value)
else
DoWriteGPU(size, address & GPU_MASK, value);
return 1;
return 0;
}
else if (address < (MDEC_BASE + MDEC_SIZE))
{
@ -194,7 +202,7 @@ TickCount Bus::DispatchAccess(PhysicalMemoryAddress address, u32& value)
else
DoWriteMDEC(size, address & MDEC_MASK, value);
return 1;
return 0;
}
else if (address < SPU_BASE)
{
@ -203,11 +211,15 @@ TickCount Bus::DispatchAccess(PhysicalMemoryAddress address, u32& value)
else if (address < (SPU_BASE + SPU_SIZE))
{
if constexpr (type == MemoryAccessType::Read)
{
value = DoReadSPU(size, address & SPU_MASK);
return m_spu_access_time[static_cast<u32>(size)];
}
else
{
DoWriteSPU(size, address & SPU_MASK, value);
return m_spu_access_time[static_cast<u32>(size)];
return 0;
}
}
else if (address < EXP2_BASE)
{
@ -216,11 +228,15 @@ TickCount Bus::DispatchAccess(PhysicalMemoryAddress address, u32& value)
else if (address < (EXP2_BASE + EXP2_SIZE))
{
if constexpr (type == MemoryAccessType::Read)
{
value = DoReadEXP2(size, address & EXP2_MASK);
return m_exp2_access_time[static_cast<u32>(size)];
}
else
{
DoWriteEXP2(size, address & EXP2_MASK, value);
return m_exp2_access_time[static_cast<u32>(size)];
return 0;
}
}
else if (address < BIOS_BASE)
{