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Bus: Reduce RAM write delay

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This commit is contained in:
Connor McLaughlin
2019-11-27 00:01:47 +10:00
parent b3cf18b593
commit aec01d3890
6 changed files with 64 additions and 41 deletions
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10
src/core/cpu_core.inl
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@ -15,14 +15,14 @@ TickCount Core::DoMemoryAccess(VirtualMemoryAddress address, u32& value)
if constexpr (type == MemoryAccessType::Write)
{
if (m_cop0_regs.sr.Isc)
return 1;
return 0;
}
const PhysicalMemoryAddress phys_addr = address & UINT32_C(0x1FFFFFFF);
if ((phys_addr & DCACHE_LOCATION_MASK) == DCACHE_LOCATION)
{
DoScratchpadAccess<type, size>(phys_addr, value);
return 1;
return 0;
}
return m_bus->DispatchAccess<type, size>(phys_addr, value);
@ -41,14 +41,14 @@ TickCount Core::DoMemoryAccess(VirtualMemoryAddress address, u32& value)
if constexpr (type == MemoryAccessType::Write)
{
if (m_cop0_regs.sr.Isc)
return 1;
return 0;
}
const PhysicalMemoryAddress phys_addr = address & UINT32_C(0x1FFFFFFF);
if ((phys_addr & DCACHE_LOCATION_MASK) == DCACHE_LOCATION)
{
DoScratchpadAccess<type, size>(phys_addr, value);
return 1;
return 0;
}
return m_bus->DispatchAccess<type, size>(phys_addr, value);
@ -72,7 +72,7 @@ TickCount Core::DoMemoryAccess(VirtualMemoryAddress address, u32& value)
else
WriteCacheControl(value);
return 1;
return 0;
}
else
{