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CPU/NewRec: Allocate callee-saved before flush in lwx/swx

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It might move a callee-saved -> caller-saved reg, in which case it's
going to get clobbered when the loadstore function is called.

SaGa Frontier 2 with PGXP on x64.
This commit is contained in:
Stenzek 2023-12-05 00:21:01 +10:00
parent 601d8ff629
commit b166ec3403
No known key found for this signature in database
4 changed files with 16 additions and 8 deletions
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6
src/core/cpu_newrec_compiler_aarch32.cpp
View File

@ -1576,6 +1576,8 @@ void CPU::NewRec::AArch32Compiler::Compile_lwx(CompileFlags cf, MemoryAccessSize
const std::optional<VirtualMemoryAddress>& address) const std::optional<VirtualMemoryAddress>& address)
{ {
DebugAssert(size == MemoryAccessSize::Word && !sign); DebugAssert(size == MemoryAccessSize::Word && !sign);
const Register addr = Register(AllocateTempHostReg(HR_CALLEE_SAVED));
FlushForLoadStore(address, false, use_fastmem); FlushForLoadStore(address, false, use_fastmem);
// TODO: if address is constant, this can be simplified.. // TODO: if address is constant, this can be simplified..
@ -1585,7 +1587,6 @@ void CPU::NewRec::AArch32Compiler::Compile_lwx(CompileFlags cf, MemoryAccessSize
UpdateLoadDelay(); UpdateLoadDelay();
// We'd need to be careful here if we weren't overwriting it.. // We'd need to be careful here if we weren't overwriting it..
const Register addr = Register(AllocateHostReg(HR_CALLEE_SAVED, HR_TYPE_TEMP));
ComputeLoadStoreAddressArg(cf, address, addr); ComputeLoadStoreAddressArg(cf, address, addr);
armAsm->and_(RARG1, addr, armCheckLogicalConstant(~0x3u)); armAsm->and_(RARG1, addr, armCheckLogicalConstant(~0x3u));
GenerateLoad(RARG1, MemoryAccessSize::Word, false, use_fastmem, []() { return RRET; }); GenerateLoad(RARG1, MemoryAccessSize::Word, false, use_fastmem, []() { return RRET; });
@ -1768,11 +1769,12 @@ void CPU::NewRec::AArch32Compiler::Compile_swx(CompileFlags cf, MemoryAccessSize
const std::optional<VirtualMemoryAddress>& address) const std::optional<VirtualMemoryAddress>& address)
{ {
DebugAssert(size == MemoryAccessSize::Word && !sign); DebugAssert(size == MemoryAccessSize::Word && !sign);
const Register addr = Register(AllocateTempHostReg(HR_CALLEE_SAVED));
FlushForLoadStore(address, true, use_fastmem); FlushForLoadStore(address, true, use_fastmem);
// TODO: if address is constant, this can be simplified.. // TODO: if address is constant, this can be simplified..
// We'd need to be careful here if we weren't overwriting it.. // We'd need to be careful here if we weren't overwriting it..
const Register addr = Register(AllocateHostReg(HR_CALLEE_SAVED, HR_TYPE_TEMP));
ComputeLoadStoreAddressArg(cf, address, addr); ComputeLoadStoreAddressArg(cf, address, addr);
armAsm->and_(RARG1, addr, armCheckLogicalConstant(~0x3u)); armAsm->and_(RARG1, addr, armCheckLogicalConstant(~0x3u));
GenerateLoad(RARG1, MemoryAccessSize::Word, false, use_fastmem, []() { return RRET; }); GenerateLoad(RARG1, MemoryAccessSize::Word, false, use_fastmem, []() { return RRET; });

6
src/core/cpu_newrec_compiler_aarch64.cpp
View File

@ -1555,6 +1555,8 @@ void CPU::NewRec::AArch64Compiler::Compile_lwx(CompileFlags cf, MemoryAccessSize
const std::optional<VirtualMemoryAddress>& address) const std::optional<VirtualMemoryAddress>& address)
{ {
DebugAssert(size == MemoryAccessSize::Word && !sign); DebugAssert(size == MemoryAccessSize::Word && !sign);
const WRegister addr = WRegister(AllocateTempHostReg(HR_CALLEE_SAVED));
FlushForLoadStore(address, false, use_fastmem); FlushForLoadStore(address, false, use_fastmem);
// TODO: if address is constant, this can be simplified.. // TODO: if address is constant, this can be simplified..
@ -1564,7 +1566,6 @@ void CPU::NewRec::AArch64Compiler::Compile_lwx(CompileFlags cf, MemoryAccessSize
UpdateLoadDelay(); UpdateLoadDelay();
// We'd need to be careful here if we weren't overwriting it.. // We'd need to be careful here if we weren't overwriting it..
const WRegister addr = WRegister(AllocateHostReg(HR_CALLEE_SAVED, HR_TYPE_TEMP));
ComputeLoadStoreAddressArg(cf, address, addr); ComputeLoadStoreAddressArg(cf, address, addr);
armAsm->and_(RWARG1, addr, armCheckLogicalConstant(~0x3u)); armAsm->and_(RWARG1, addr, armCheckLogicalConstant(~0x3u));
GenerateLoad(RWARG1, MemoryAccessSize::Word, false, use_fastmem, []() { return RWRET; }); GenerateLoad(RWARG1, MemoryAccessSize::Word, false, use_fastmem, []() { return RWRET; });
@ -1747,11 +1748,12 @@ void CPU::NewRec::AArch64Compiler::Compile_swx(CompileFlags cf, MemoryAccessSize
const std::optional<VirtualMemoryAddress>& address) const std::optional<VirtualMemoryAddress>& address)
{ {
DebugAssert(size == MemoryAccessSize::Word && !sign); DebugAssert(size == MemoryAccessSize::Word && !sign);
const WRegister addr = WRegister(AllocateTempHostReg(HR_CALLEE_SAVED));
FlushForLoadStore(address, true, use_fastmem); FlushForLoadStore(address, true, use_fastmem);
// TODO: if address is constant, this can be simplified.. // TODO: if address is constant, this can be simplified..
// We'd need to be careful here if we weren't overwriting it.. // We'd need to be careful here if we weren't overwriting it..
const WRegister addr = WRegister(AllocateHostReg(HR_CALLEE_SAVED, HR_TYPE_TEMP));
ComputeLoadStoreAddressArg(cf, address, addr); ComputeLoadStoreAddressArg(cf, address, addr);
armAsm->and_(RWARG1, addr, armCheckLogicalConstant(~0x3u)); armAsm->and_(RWARG1, addr, armCheckLogicalConstant(~0x3u));
GenerateLoad(RWARG1, MemoryAccessSize::Word, false, use_fastmem, []() { return RWRET; }); GenerateLoad(RWARG1, MemoryAccessSize::Word, false, use_fastmem, []() { return RWRET; });

6
src/core/cpu_newrec_compiler_riscv64.cpp
View File

@ -1847,6 +1847,8 @@ void CPU::NewRec::RISCV64Compiler::Compile_lwx(CompileFlags cf, MemoryAccessSize
const std::optional<VirtualMemoryAddress>& address) const std::optional<VirtualMemoryAddress>& address)
{ {
DebugAssert(size == MemoryAccessSize::Word && !sign); DebugAssert(size == MemoryAccessSize::Word && !sign);
const GPR addr = GPR(AllocateTempHostReg(HR_CALLEE_SAVED));
FlushForLoadStore(address, false, use_fastmem); FlushForLoadStore(address, false, use_fastmem);
// TODO: if address is constant, this can be simplified.. // TODO: if address is constant, this can be simplified..
@ -1856,7 +1858,6 @@ void CPU::NewRec::RISCV64Compiler::Compile_lwx(CompileFlags cf, MemoryAccessSize
UpdateLoadDelay(); UpdateLoadDelay();
// We'd need to be careful here if we weren't overwriting it.. // We'd need to be careful here if we weren't overwriting it..
const GPR addr = GPR(AllocateHostReg(HR_CALLEE_SAVED, HR_TYPE_TEMP));
ComputeLoadStoreAddressArg(cf, address, addr); ComputeLoadStoreAddressArg(cf, address, addr);
rvAsm->ANDI(RARG1, addr, ~0x3u); rvAsm->ANDI(RARG1, addr, ~0x3u);
GenerateLoad(RARG1, MemoryAccessSize::Word, false, use_fastmem, []() { return RRET; }); GenerateLoad(RARG1, MemoryAccessSize::Word, false, use_fastmem, []() { return RRET; });
@ -2012,11 +2013,12 @@ void CPU::NewRec::RISCV64Compiler::Compile_swx(CompileFlags cf, MemoryAccessSize
const std::optional<VirtualMemoryAddress>& address) const std::optional<VirtualMemoryAddress>& address)
{ {
DebugAssert(size == MemoryAccessSize::Word && !sign); DebugAssert(size == MemoryAccessSize::Word && !sign);
const GPR addr = GPR(AllocateTempHostReg(HR_CALLEE_SAVED));
FlushForLoadStore(address, true, use_fastmem); FlushForLoadStore(address, true, use_fastmem);
// TODO: if address is constant, this can be simplified.. // TODO: if address is constant, this can be simplified..
// We'd need to be careful here if we weren't overwriting it.. // We'd need to be careful here if we weren't overwriting it..
const GPR addr = GPR(AllocateHostReg(HR_CALLEE_SAVED, HR_TYPE_TEMP));
ComputeLoadStoreAddressArg(cf, address, addr); ComputeLoadStoreAddressArg(cf, address, addr);
rvAsm->ANDI(RARG1, addr, ~0x3u); rvAsm->ANDI(RARG1, addr, ~0x3u);
GenerateLoad(RARG1, MemoryAccessSize::Word, false, use_fastmem, []() { return RRET; }); GenerateLoad(RARG1, MemoryAccessSize::Word, false, use_fastmem, []() { return RRET; });

6
src/core/cpu_newrec_compiler_x64.cpp
View File

@ -1515,6 +1515,8 @@ void CPU::NewRec::X64Compiler::Compile_lwx(CompileFlags cf, MemoryAccessSize siz
const std::optional<VirtualMemoryAddress>& address) const std::optional<VirtualMemoryAddress>& address)
{ {
DebugAssert(size == MemoryAccessSize::Word && !sign); DebugAssert(size == MemoryAccessSize::Word && !sign);
const Reg32 addr = Reg32(AllocateTempHostReg(HR_CALLEE_SAVED));
FlushForLoadStore(address, false, use_fastmem); FlushForLoadStore(address, false, use_fastmem);
// TODO: if address is constant, this can be simplified.. // TODO: if address is constant, this can be simplified..
@ -1524,7 +1526,6 @@ void CPU::NewRec::X64Compiler::Compile_lwx(CompileFlags cf, MemoryAccessSize siz
UpdateLoadDelay(); UpdateLoadDelay();
// We'd need to be careful here if we weren't overwriting it.. // We'd need to be careful here if we weren't overwriting it..
const Reg32 addr = Reg32(AllocateHostReg(HR_CALLEE_SAVED, HR_TYPE_TEMP));
ComputeLoadStoreAddressArg(cf, address, addr); ComputeLoadStoreAddressArg(cf, address, addr);
cg->mov(RWARG1, addr); cg->mov(RWARG1, addr);
cg->and_(RWARG1, ~0x3u); cg->and_(RWARG1, ~0x3u);
@ -1711,11 +1712,12 @@ void CPU::NewRec::X64Compiler::Compile_swx(CompileFlags cf, MemoryAccessSize siz
const std::optional<VirtualMemoryAddress>& address) const std::optional<VirtualMemoryAddress>& address)
{ {
DebugAssert(size == MemoryAccessSize::Word && !sign); DebugAssert(size == MemoryAccessSize::Word && !sign);
const Reg32 addr = Reg32(AllocateTempHostReg(HR_CALLEE_SAVED));
FlushForLoadStore(address, true, use_fastmem); FlushForLoadStore(address, true, use_fastmem);
// TODO: if address is constant, this can be simplified.. // TODO: if address is constant, this can be simplified..
// We'd need to be careful here if we weren't overwriting it.. // We'd need to be careful here if we weren't overwriting it..
const Reg32 addr = Reg32(AllocateHostReg(HR_CALLEE_SAVED, HR_TYPE_TEMP));
ComputeLoadStoreAddressArg(cf, address, addr); ComputeLoadStoreAddressArg(cf, address, addr);
cg->mov(RWARG1, addr); cg->mov(RWARG1, addr);
cg->and_(RWARG1, ~0x3u); cg->and_(RWARG1, ~0x3u);