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dep: Add vixl (AArch32/64 assembler)
This commit is contained in:
Connor McLaughlin
541
dep/vixl/include/vixl/aarch32/constants-aarch32.h
Normal file
541
dep/vixl/include/vixl/aarch32/constants-aarch32.h
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@ -0,0 +1,541 @@
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// Copyright 2015, VIXL authors
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// * Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// * Neither the name of ARM Limited nor the names of its contributors may
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// be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
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// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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#ifndef VIXL_CONSTANTS_AARCH32_H_
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#define VIXL_CONSTANTS_AARCH32_H_
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extern "C" {
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#include <stdint.h>
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}
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#include "globals-vixl.h"
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namespace vixl {
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namespace aarch32 {
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enum InstructionSet { A32, T32 };
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#ifdef VIXL_INCLUDE_TARGET_T32_ONLY
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const InstructionSet kDefaultISA = T32;
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#else
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const InstructionSet kDefaultISA = A32;
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#endif
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const unsigned kRegSizeInBits = 32;
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const unsigned kRegSizeInBytes = kRegSizeInBits / 8;
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const unsigned kSRegSizeInBits = 32;
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const unsigned kSRegSizeInBytes = kSRegSizeInBits / 8;
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const unsigned kDRegSizeInBits = 64;
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const unsigned kDRegSizeInBytes = kDRegSizeInBits / 8;
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const unsigned kQRegSizeInBits = 128;
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const unsigned kQRegSizeInBytes = kQRegSizeInBits / 8;
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const unsigned kNumberOfRegisters = 16;
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const unsigned kNumberOfSRegisters = 32;
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const unsigned kMaxNumberOfDRegisters = 32;
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const unsigned kNumberOfQRegisters = 16;
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const unsigned kNumberOfT32LowRegisters = 8;
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const unsigned kIpCode = 12;
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const unsigned kSpCode = 13;
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const unsigned kLrCode = 14;
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const unsigned kPcCode = 15;
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const unsigned kT32PcDelta = 4;
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const unsigned kA32PcDelta = 8;
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const unsigned kRRXEncodedValue = 3;
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const unsigned kCoprocMask = 0xe;
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const unsigned kInvalidCoprocMask = 0xa;
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const unsigned kLowestT32_32Opcode = 0xe8000000;
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const uint32_t kUnknownValue = 0xdeadbeef;
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const uint32_t kMaxInstructionSizeInBytes = 4;
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const uint32_t kA32InstructionSizeInBytes = 4;
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const uint32_t k32BitT32InstructionSizeInBytes = 4;
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const uint32_t k16BitT32InstructionSizeInBytes = 2;
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// Maximum size emitted by a single T32 unconditional macro-instruction.
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const uint32_t kMaxT32MacroInstructionSizeInBytes = 32;
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const uint32_t kCallerSavedRegistersMask = 0x500f;
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const uint16_t k16BitT32NopOpcode = 0xbf00;
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const uint16_t kCbzCbnzMask = 0xf500;
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const uint16_t kCbzCbnzValue = 0xb100;
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const int32_t kCbzCbnzRange = 126;
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const int32_t kBConditionalNarrowRange = 254;
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const int32_t kBNarrowRange = 2046;
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const int32_t kNearLabelRange = kBNarrowRange;
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enum SystemFunctionsOpcodes { kPrintfCode };
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enum BranchHint { kNear, kFar, kBranchWithoutHint };
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// Start of generated code.
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// AArch32 version implemented by the library (v8.0).
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// The encoding for vX.Y is: (X << 8) | Y.
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#define AARCH32_VERSION 0x0800
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enum InstructionAttribute {
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kNoAttribute = 0,
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kArithmetic = 0x1,
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kBitwise = 0x2,
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kShift = 0x4,
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kAddress = 0x8,
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kBranch = 0x10,
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kSystem = 0x20,
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kFpNeon = 0x40,
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kLoadStore = 0x80,
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kLoadStoreMultiple = 0x100
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};
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enum InstructionType {
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kUndefInstructionType,
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kAdc,
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kAdcs,
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kAdd,
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kAdds,
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kAddw,
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kAdr,
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kAnd,
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kAnds,
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kAsr,
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kAsrs,
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kB,
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kBfc,
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kBfi,
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kBic,
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kBics,
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kBkpt,
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kBl,
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kBlx,
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kBx,
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kBxj,
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kCbnz,
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kCbz,
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kClrex,
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kClz,
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kCmn,
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kCmp,
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kCrc32b,
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kCrc32cb,
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kCrc32ch,
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kCrc32cw,
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kCrc32h,
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kCrc32w,
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kDmb,
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kDsb,
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kEor,
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kEors,
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kFldmdbx,
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kFldmiax,
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kFstmdbx,
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kFstmiax,
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kHlt,
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kHvc,
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kIsb,
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kIt,
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kLda,
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kLdab,
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kLdaex,
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kLdaexb,
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kLdaexd,
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kLdaexh,
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kLdah,
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kLdm,
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kLdmda,
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kLdmdb,
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kLdmea,
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kLdmed,
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kLdmfa,
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kLdmfd,
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kLdmib,
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kLdr,
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kLdrb,
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kLdrd,
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kLdrex,
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kLdrexb,
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kLdrexd,
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kLdrexh,
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kLdrh,
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kLdrsb,
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kLdrsh,
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kLsl,
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kLsls,
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kLsr,
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kLsrs,
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kMla,
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kMlas,
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kMls,
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kMov,
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kMovs,
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kMovt,
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kMovw,
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kMrs,
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kMsr,
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kMul,
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kMuls,
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kMvn,
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kMvns,
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kNop,
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kOrn,
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kOrns,
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kOrr,
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kOrrs,
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kPkhbt,
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kPkhtb,
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kPld,
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kPldw,
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kPli,
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kPop,
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kPush,
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kQadd,
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kQadd16,
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kQadd8,
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kQasx,
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kQdadd,
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kQdsub,
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kQsax,
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kQsub,
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kQsub16,
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kQsub8,
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kRbit,
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kRev,
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kRev16,
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kRevsh,
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kRor,
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kRors,
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kRrx,
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kRrxs,
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kRsb,
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kRsbs,
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kRsc,
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kRscs,
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kSadd16,
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kSadd8,
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kSasx,
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kSbc,
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kSbcs,
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kSbfx,
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kSdiv,
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kSel,
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kShadd16,
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kShadd8,
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kShasx,
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kShsax,
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kShsub16,
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kShsub8,
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kSmlabb,
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kSmlabt,
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kSmlad,
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kSmladx,
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kSmlal,
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kSmlalbb,
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kSmlalbt,
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kSmlald,
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kSmlaldx,
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kSmlals,
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kSmlaltb,
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kSmlaltt,
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kSmlatb,
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kSmlatt,
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kSmlawb,
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kSmlawt,
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kSmlsd,
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kSmlsdx,
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kSmlsld,
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kSmlsldx,
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kSmmla,
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kSmmlar,
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kSmmls,
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kSmmlsr,
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kSmmul,
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kSmmulr,
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kSmuad,
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kSmuadx,
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kSmulbb,
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kSmulbt,
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kSmull,
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kSmulls,
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kSmultb,
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kSmultt,
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kSmulwb,
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kSmulwt,
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kSmusd,
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kSmusdx,
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kSsat,
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kSsat16,
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kSsax,
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kSsub16,
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kSsub8,
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kStl,
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kStlb,
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kStlex,
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kStlexb,
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kStlexd,
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kStlexh,
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kStlh,
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kStm,
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kStmda,
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kStmdb,
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kStmea,
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kStmed,
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kStmfa,
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kStmfd,
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kStmib,
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kStr,
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kStrb,
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kStrd,
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kStrex,
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kStrexb,
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kStrexd,
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kStrexh,
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kStrh,
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kSub,
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kSubs,
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kSubw,
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kSvc,
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kSxtab,
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kSxtab16,
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kSxtah,
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kSxtb,
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kSxtb16,
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kSxth,
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kTbb,
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kTbh,
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kTeq,
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kTst,
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kUadd16,
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kUadd8,
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kUasx,
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kUbfx,
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kUdf,
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kUdiv,
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kUhadd16,
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kUhadd8,
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kUhasx,
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kUhsax,
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kUhsub16,
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kUhsub8,
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kUmaal,
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kUmlal,
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kUmlals,
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kUmull,
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kUmulls,
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kUqadd16,
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kUqadd8,
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kUqasx,
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kUqsax,
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kUqsub16,
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kUqsub8,
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kUsad8,
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kUsada8,
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kUsat,
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kUsat16,
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kUsax,
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kUsub16,
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kUsub8,
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kUxtab,
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kUxtab16,
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kUxtah,
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kUxtb,
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kUxtb16,
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kUxth,
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kVaba,
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kVabal,
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kVabd,
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kVabdl,
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kVabs,
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kVacge,
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kVacgt,
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kVacle,
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kVaclt,
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kVadd,
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kVaddhn,
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kVaddl,
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kVaddw,
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kVand,
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kVbic,
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kVbif,
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kVbit,
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kVbsl,
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kVceq,
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kVcge,
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kVcgt,
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kVcle,
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kVcls,
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kVclt,
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kVclz,
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kVcmp,
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kVcmpe,
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kVcnt,
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kVcvt,
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kVcvta,
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kVcvtb,
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kVcvtm,
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kVcvtn,
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kVcvtp,
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kVcvtr,
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kVcvtt,
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kVdiv,
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kVdup,
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kVeor,
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kVext,
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kVfma,
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kVfms,
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kVfnma,
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kVfnms,
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kVhadd,
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kVhsub,
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kVld1,
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kVld2,
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kVld3,
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kVld4,
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kVldm,
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kVldmdb,
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kVldmia,
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kVldr,
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kVmax,
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kVmaxnm,
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kVmin,
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kVminnm,
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kVmla,
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kVmlal,
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kVmls,
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kVmlsl,
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kVmov,
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kVmovl,
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kVmovn,
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kVmrs,
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kVmsr,
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kVmul,
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kVmull,
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kVmvn,
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kVneg,
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kVnmla,
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kVnmls,
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kVnmul,
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kVorn,
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kVorr,
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kVpadal,
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kVpadd,
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kVpaddl,
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kVpmax,
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kVpmin,
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kVpop,
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kVpush,
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kVqabs,
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kVqadd,
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kVqdmlal,
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kVqdmlsl,
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kVqdmulh,
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kVqdmull,
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kVqmovn,
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kVqmovun,
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kVqneg,
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kVqrdmulh,
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kVqrshl,
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kVqrshrn,
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kVqrshrun,
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kVqshl,
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kVqshlu,
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kVqshrn,
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kVqshrun,
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kVqsub,
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kVraddhn,
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kVrecpe,
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kVrecps,
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kVrev16,
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kVrev32,
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kVrev64,
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kVrhadd,
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kVrinta,
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kVrintm,
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kVrintn,
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kVrintp,
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kVrintr,
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kVrintx,
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kVrintz,
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kVrshl,
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kVrshr,
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kVrshrn,
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kVrsqrte,
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kVrsqrts,
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kVrsra,
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kVrsubhn,
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kVseleq,
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kVselge,
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kVselgt,
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kVselvs,
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kVshl,
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kVshll,
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kVshr,
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kVshrn,
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kVsli,
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kVsqrt,
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kVsra,
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kVsri,
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kVst1,
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kVst2,
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kVst3,
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kVst4,
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kVstm,
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kVstmdb,
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kVstmia,
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kVstr,
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kVsub,
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kVsubhn,
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kVsubl,
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kVsubw,
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kVswp,
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kVtbl,
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kVtbx,
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kVtrn,
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kVtst,
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kVuzp,
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kVzip,
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kYield
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};
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const char* ToCString(InstructionType type);
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// End of generated code.
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inline InstructionAttribute operator|(InstructionAttribute left,
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InstructionAttribute right) {
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return static_cast<InstructionAttribute>(static_cast<uint32_t>(left) |
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static_cast<uint32_t>(right));
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}
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} // namespace aarch32
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} // namespace vixl
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#endif // VIXL_CONSTANTS_AARCH32_H_
|
||||
Reference in New Issue
Block a user