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82 Commits

Author SHA1 Message Date
Stenzek
84e5fbe0c6 CPU: HLE implementation of PCDrv (host file access) 2023-04-29 20:45:39 +10:00
Connor McLaughlin
fe08d34e52 Qt: Add COP0/GTE registers to debugger list 2023-01-15 15:13:54 +10:00
Connor McLaughlin
8c7a192128 Misc: Add copyright/license statement to applicable files 
Should've did this in the beginning.
 2022-12-04 21:03:49 +10:00
Connor McLaughlin
b42b5501f6 UI: Massive revamp, new features and improvements 2022-07-22 21:19:54 +10:00
Connor McLaughlin
b7fbde31a7 Move utility classes from common to own static lib 2022-07-21 17:29:58 +10:00
Connor McLaughlin
46737acecd CPU: Prevent mismatched va_start/va_end in log 2022-01-06 22:47:10 +10:00
Connor McLaughlin
bbf67ef544 CPU: Warning fix 2021-12-25 14:28:32 +10:00
Connor McLaughlin
53299e3c7b CPU/Interpreter: Load delay check should be a debug assertion 2021-07-24 13:04:54 +10:00
Connor McLaughlin
30db081a64 CPU: Simulate stalls from GTE instructions 2021-07-16 12:27:31 +10:00
Connor McLaughlin
4f09d61825 CPU: Don't panic on invalid instructions 2021-06-15 22:58:29 +10:00
Connor McLaughlin
1ed1d641a6 CPU/Recompiler: Don't use intepreter icache when falling back 
Fixes broken rendering in TOCA 2.

It has self-modifying code every frame, which gets falled back to the
interpreter, and using the interpreter's icache, which resulted in
stale code executing.
 2021-05-20 12:19:23 +10:00
Connor McLaughlin
e382df0d41 Support expanding RAM to 8MB (dev console) 2021-05-03 12:43:33 +10:00
Connor McLaughlin
f1310bf93a System: Don't discard PGXP state when runahead-rollbacking 
You'll still see some glitches if you have the frame count set too high,
since you'll get imprecise values for any vertices which have moved, but
that's going to happen anyway because of the runahead in the first
place.
 2021-04-28 02:51:44 +10:00
Connor McLaughlin
40731b49fc Bus: Handle CPU-internal narrow writes 
The full 32-bits of the GPR are used.

Fixes SoundScope in the BIOS Shell.
 2021-04-26 22:08:18 +10:00
Connor McLaughlin
3106c797d9 CPU: Reduce severity of some log statements 2021-04-19 15:19:08 +10:00
Connor McLaughlin
442b801d39 CPU: Implement cop0 execution and data breakpoints 2021-04-14 19:06:52 +10:00
Connor McLaughlin
22fdd80cc3 CPU/Interpreter: Out of range cop0 reads should be nops 2021-04-14 19:06:52 +10:00
Connor McLaughlin
dd5277321b CPU/CachedInterpreter: Fix infinite loop when block compile fails 2021-04-14 19:06:52 +10:00
Connor McLaughlin
e087e6f3a2 CPU/Recompiler: Prevent using fastmem when cache is isolated 
No point even trying since it's just going to fault.
 2021-04-12 02:08:56 +10:00
Connor McLaughlin
922d320523 CPU/Recompiler: Reserve whole fastmem region to avoid clashes 2021-04-11 12:42:51 +10:00
Connor McLaughlin
209827b67c PGXP: Compute PSX values on demand for CPU instructions 
Generates shorter code for the recompiler.
 2021-02-18 02:08:48 +10:00
Connor McLaughlin
1b881fc60b PGXP: Combine instr and rtVal parameters for CPU_LUI 2021-02-18 02:08:47 +10:00
Connor McLaughlin
0bfa1bf873 PGXP: Fix MFC0/MTC0 
Doubt it'll change anything.
 2021-02-18 02:08:47 +10:00
Connor McLaughlin
a722fd6b53 PGXP: Make mult/div compute results instead of parameters 
Lets us call it from the recompiler.
 2021-02-18 02:08:47 +10:00
Connor McLaughlin
33a5617ea3 PGXP: Remove some unused parameter from M{F,T}{HI,LO} 2021-02-18 02:08:47 +10:00
Connor McLaughlin
efecb44344 PGXP: Combine a couple of instructions 2021-02-18 02:08:47 +10:00
Connor McLaughlin
9d80c48d6f CPU: Fix icache missing from save state 2021-01-31 16:39:51 +10:00
Connor McLaughlin
e3262fc0a4 CPU: Compile fix for debug builds 2021-01-05 00:46:41 +10:00
Connor McLaughlin
9ff8130e40 fixup! CPU: Make trace-to-file toggleable at runtime and in release builds 2021-01-04 03:11:14 +10:00
Connor McLaughlin
bf1d51b5d8 CPU: Make trace-to-file toggleable at runtime and in release builds 2021-01-04 03:11:14 +10:00
Connor McLaughlin
c9240eea72 CPU/Recompiler: Use PGXP interpreter for fallback 
Fixes holes in geometry with PGXP enabled in Threads of Fate.
 2021-01-01 17:16:55 +10:00
Connor McLaughlin
3b23542ec9 CPU: Provide debugger/breakpoint/step functionality 2020-12-17 11:57:47 +10:00
Connor McLaughlin
bf2e38aed5 CPU/Recompiler: Implement LUT-based fastmem 2020-11-24 14:49:21 +10:00
Connor McLaughlin
a03bca2f72 CPU: Make fastmem a compile-time feature (support 32-bit targets) 2020-11-21 18:39:03 +10:00
Connor McLaughlin
042bdd9c0c CPU/CodeCache: Fetch second delay slot from first branch for double branches 2020-11-19 00:40:02 +10:00
Connor McLaughlin
077764ce18 CPU/Interpreter: Handle move instructions in PGXP memory mode 2020-11-14 23:20:28 +10:00
Connor McLaughlin
6cd991bc57 BIOS: Turn display on with fast boot 
Fixes black screen in SaGa Frontier with fast boot disabled.
 2020-11-11 01:02:40 +10:00
Connor McLaughlin
7566c45f64 CPU/Recompiler: Implement fastmem 2020-10-18 14:54:38 +10:00
Connor McLaughlin
a6f8dde790 CPU/Recompiler: Faster ASM dispatcher 2020-10-18 14:54:38 +10:00
Connor McLaughlin
cb351a7dbd CPU: Move interrupt check out of inner-most exec loop 2020-10-18 14:54:38 +10:00
Connor McLaughlin
fa638ef9d2 CPU/Interpreter: Fix incorrect call in to PGXP for addi 
Fixes exploding triangles in Spyro with PGXP CPU mode enabled.
 2020-10-09 18:49:36 +10:00
Connor McLaughlin
27697d0508 System: Implement CPU overclocking [SAVEVERSION+] 
Partial credit to @CookiePLMonster as well.
 2020-09-30 23:48:34 +10:00
Connor McLaughlin
25f45fbd23 CPU: Add hack for stale icache reads in interpreter 2020-09-20 01:38:18 +10:00
Connor McLaughlin
9736dc7895 CPU: Fix InterpretUncachedBlock() 
But this shouldn't be hit during normal execution.
 2020-09-20 01:36:49 +10:00
Connor McLaughlin
a2eaaf0e89 PGXP: Allocate large storage dynamically 
This causes performance issues on ARM otherwise.
 2020-09-03 00:11:40 +10:00
Connor McLaughlin
19d6037b99 CPU: Implement instruction cache simulation 
Implemented for all execution modes. Disabled by default in the cached
interpreter and recompiler, always enabled in the pure interpreter.
 2020-08-29 22:07:40 +10:00
Connor McLaughlin
d37fba81ed CPU/Interpreter: Fix incorrect downcount comparison 2020-08-23 01:41:55 +10:00
Connor McLaughlin
6a17a558bb CPU: Linux compile fix 2020-08-20 01:05:03 +10:00
Connor McLaughlin
daa72aba10 CPU: Skip executing nop instructions 
Makes PGXP CPU mode quicker, as well as a performance improvement to the
regular interpreter.
 2020-08-20 00:49:39 +10:00
Connor McLaughlin
2e9f656546 CPU: Implement PGXP CPU Mode 
This is *very* slow. You don't want to enable it if you don't need it.
It is also incompatible with the recompiler and will disable it if the
option is enabled.
 2020-08-20 00:49:39 +10:00