16 Commits

Author	SHA1	Message	Date
Connor McLaughlin	eddd2c1990	CPU: Correct bits for CAUSE.CE, EPC for fetch	2019-10-04 02:27:34 +10:00
Connor McLaughlin	1f6130f04a	CPU: Restore faster IPS	2019-10-03 16:45:54 +10:00
Connor McLaughlin	8b4ec87055	CPU: Support printing instruction operands when tracing	2019-09-30 17:32:58 +10:00
Connor McLaughlin	9359d0778e	Clean up memory access handlers, reduce template specializations	2019-09-25 00:36:24 +10:00
Connor McLaughlin	948ac50020	CPU: Refactoring, implement LWC/SWC	2019-09-22 02:06:47 +10:00
Connor McLaughlin	c988af453c	Refactor timing to allow sync/updates in the middle of a slice	2019-09-21 01:24:33 +10:00
Connor McLaughlin	4025d6e4a6	GTE: Stub and register read/write function	2019-09-17 23:38:04 +10:00
Connor McLaughlin	2128a2984b	Add interrupt controller emulation	2019-09-17 16:26:00 +10:00
Connor McLaughlin	f47688b61f	System: Basic timings for GPU scanout	2019-09-17 14:25:25 +10:00
Connor McLaughlin	540f282213	CPU: Fix incorrect exception vector for break	2019-09-15 12:43:54 +10:00
Connor McLaughlin	d58dbe04c0	CPU: Fix load delay register reads for same register in delay slot	2019-09-15 12:16:51 +10:00
Connor McLaughlin	4ca3b4b570	CPU: Fix alignment exception on register indirect branch	2019-09-15 01:13:11 +10:00
Connor McLaughlin	32a36ef1bc	CPU: Implement alignment (memory) exception	2019-09-14 14:29:23 +10:00
Connor McLaughlin	0726095f00	CPU: Implement fixed dcache/scratchpad	2019-09-14 14:18:42 +10:00
Connor McLaughlin	9f36384752	System: Support sideloading EXE files via BIOS patch	2019-09-14 13:22:34 +10:00
Connor McLaughlin	2149ab4d69	Initial commit	2019-09-11 14:00:42 +10:00