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548 lines
15 KiB
C++
548 lines
15 KiB
C++
#include "dma.h"
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#include "YBaseLib/Log.h"
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#include "bus.h"
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#include "cdrom.h"
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#include "common/state_wrapper.h"
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#include "gpu.h"
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#include "interrupt_controller.h"
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#include "mdec.h"
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#include "spu.h"
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#include "system.h"
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Log_SetChannel(DMA);
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DMA::DMA() = default;
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DMA::~DMA() = default;
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void DMA::Initialize(System* system, Bus* bus, InterruptController* interrupt_controller, GPU* gpu, CDROM* cdrom,
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SPU* spu, MDEC* mdec)
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{
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m_system = system;
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m_bus = bus;
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m_interrupt_controller = interrupt_controller;
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m_gpu = gpu;
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m_cdrom = cdrom;
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m_spu = spu;
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m_mdec = mdec;
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m_transfer_buffer.resize(32);
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}
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void DMA::Reset()
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{
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m_transfer_in_progress = false;
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std::memset(&m_state, 0, sizeof(m_state));
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m_DPCR.bits = 0x07654321;
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m_DICR.bits = 0;
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}
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bool DMA::DoState(StateWrapper& sw)
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{
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for (u32 i = 0; i < NUM_CHANNELS; i++)
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{
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ChannelState& cs = m_state[i];
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sw.Do(&cs.base_address);
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sw.Do(&cs.block_control.bits);
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sw.Do(&cs.channel_control.bits);
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sw.Do(&cs.transfer_ticks);
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sw.Do(&cs.request);
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}
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sw.Do(&m_DPCR.bits);
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sw.Do(&m_DICR.bits);
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if (sw.IsReading())
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{
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m_transfer_min_ticks = std::numeric_limits<TickCount>::max();
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for (const ChannelState& cs : m_state)
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{
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if (cs.transfer_ticks > 0)
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m_transfer_min_ticks = std::min(m_transfer_min_ticks, cs.transfer_ticks);
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}
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m_system->SetDowncount(m_transfer_min_ticks);
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}
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return !sw.HasError();
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}
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u32 DMA::ReadRegister(u32 offset)
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{
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const u32 channel_index = offset >> 4;
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if (channel_index < 7)
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{
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switch (offset & UINT32_C(0x0F))
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{
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case 0x00:
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{
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Log_TracePrintf("DMA%u base address -> 0x%08X", channel_index, m_state[channel_index].base_address);
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return m_state[channel_index].base_address;
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}
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case 0x04:
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{
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Log_TracePrintf("DMA%u block control -> 0x%08X", channel_index, m_state[channel_index].block_control.bits);
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return m_state[channel_index].block_control.bits;
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}
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case 0x08:
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{
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Log_TracePrintf("DMA%u channel control -> 0x%08X", channel_index, m_state[channel_index].channel_control.bits);
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return m_state[channel_index].channel_control.bits;
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}
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default:
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break;
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}
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}
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else
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{
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if (offset == 0x70)
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{
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Log_TracePrintf("DPCR -> 0x%08X", m_DPCR.bits);
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return m_DPCR.bits;
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}
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else if (offset == 0x74)
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{
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Log_TracePrintf("DPCR -> 0x%08X", m_DPCR.bits);
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return m_DICR.bits;
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}
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}
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Log_ErrorPrintf("Unhandled register read: %02X", offset);
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return UINT32_C(0xFFFFFFFF);
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}
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void DMA::WriteRegister(u32 offset, u32 value)
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{
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const u32 channel_index = offset >> 4;
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if (channel_index < 7)
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{
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ChannelState& state = m_state[channel_index];
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switch (offset & UINT32_C(0x0F))
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{
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case 0x00:
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{
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state.base_address = value & BASE_ADDRESS_MASK;
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Log_TracePrintf("DMA channel %u base address <- 0x%08X", channel_index, state.base_address);
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return;
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}
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case 0x04:
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{
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Log_TracePrintf("DMA channel %u block control <- 0x%08X", channel_index, value);
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state.block_control.bits = value;
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QueueTransferChannel(static_cast<Channel>(channel_index));
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return;
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}
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case 0x08:
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{
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state.channel_control.bits = (state.channel_control.bits & ~ChannelState::ChannelControl::WRITE_MASK) |
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(value & ChannelState::ChannelControl::WRITE_MASK);
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Log_TracePrintf("DMA channel %u channel control <- 0x%08X", channel_index, state.channel_control.bits);
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QueueTransferChannel(static_cast<Channel>(channel_index));
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return;
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}
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default:
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break;
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}
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}
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else
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{
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switch (offset)
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{
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case 0x70:
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{
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Log_TracePrintf("DPCR <- 0x%08X", value);
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m_DPCR.bits = value;
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QueueTransfer();
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return;
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}
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case 0x74:
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{
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Log_TracePrintf("DCIR <- 0x%08X", value);
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m_DICR.bits = (m_DICR.bits & ~DICR_WRITE_MASK) | (value & DICR_WRITE_MASK);
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m_DICR.bits = m_DICR.bits & ~(value & DICR_RESET_MASK);
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m_DICR.UpdateMasterFlag();
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return;
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}
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default:
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break;
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}
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}
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Log_ErrorPrintf("Unhandled register write: %02X <- %08X", offset, value);
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}
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void DMA::SetRequest(Channel channel, bool request)
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{
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ChannelState& cs = m_state[static_cast<u32>(channel)];
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if (cs.request == request)
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return;
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cs.request = request;
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if (request)
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QueueTransfer();
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}
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TickCount DMA::GetTransferDelay(Channel channel) const
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{
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const ChannelState& cs = m_state[static_cast<u32>(channel)];
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switch (channel)
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{
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case Channel::SPU:
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{
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if (cs.channel_control.sync_mode == SyncMode::Request)
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return (cs.block_control.request.GetBlockCount() * (cs.block_control.request.GetBlockSize() / 2));
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else
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return 1;
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}
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break;
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default:
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return 1;
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}
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}
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bool DMA::CanTransferChannel(Channel channel) const
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{
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if (!m_DPCR.GetMasterEnable(channel))
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return false;
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const ChannelState& cs = m_state[static_cast<u32>(channel)];
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if (!cs.channel_control.enable_busy)
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return false;
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if (!cs.request && channel != Channel::OTC)
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return false;
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if (cs.channel_control.sync_mode == SyncMode::Manual && !cs.channel_control.start_trigger)
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return false;
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if (cs.transfer_ticks > 0)
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return false;
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return true;
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}
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bool DMA::CanRunAnyChannels() const
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{
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for (u32 i = 0; i < NUM_CHANNELS; i++)
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{
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if (CanTransferChannel(static_cast<Channel>(i)))
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return true;
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}
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return false;
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}
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void DMA::UpdateIRQ()
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{
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m_DICR.UpdateMasterFlag();
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if (m_DICR.master_flag)
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{
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Log_TracePrintf("Firing DMA master interrupt");
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m_interrupt_controller->InterruptRequest(InterruptController::IRQ::DMA);
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}
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}
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void DMA::QueueTransferChannel(Channel channel)
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{
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ChannelState& cs = m_state[static_cast<u32>(channel)];
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if (cs.transfer_ticks > 0 || !CanTransferChannel(channel))
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return;
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const TickCount ticks = GetTransferDelay(channel);
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if (ticks == 0)
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{
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// immediate transfer
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TransferChannel(channel);
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return;
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}
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if (!m_transfer_in_progress)
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m_system->Synchronize();
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cs.transfer_ticks = ticks;
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m_transfer_min_ticks = std::min(m_transfer_min_ticks, ticks);
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m_system->SetDowncount(ticks);
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}
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void DMA::QueueTransfer()
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{
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for (u32 i = 0; i < NUM_CHANNELS; i++)
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QueueTransferChannel(static_cast<Channel>(i));
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}
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void DMA::Execute(TickCount ticks)
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{
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m_transfer_min_ticks -= ticks;
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if (m_transfer_min_ticks > 0)
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{
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m_system->SetDowncount(m_transfer_min_ticks);
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return;
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}
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DebugAssert(!m_transfer_in_progress);
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m_transfer_in_progress = true;
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// keep going until all transfers are done. one channel can start others (e.g. MDEC)
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m_transfer_min_ticks = std::numeric_limits<TickCount>::max();
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for (u32 i = 0; i < NUM_CHANNELS; i++)
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{
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const Channel channel = static_cast<Channel>(i);
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if (m_state[i].transfer_ticks <= 0)
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continue;
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m_state[i].transfer_ticks -= ticks;
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if (CanTransferChannel(channel))
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{
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TransferChannel(channel);
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}
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else
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{
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m_transfer_min_ticks = std::min(m_transfer_min_ticks, ticks);
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}
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}
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m_system->SetDowncount(m_transfer_min_ticks);
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m_transfer_in_progress = false;
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}
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void DMA::TransferChannel(Channel channel)
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{
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ChannelState& cs = m_state[static_cast<u32>(channel)];
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const bool copy_to_device = cs.channel_control.copy_to_device;
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// start/trigger bit is cleared on beginning of transfer
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cs.channel_control.start_trigger = false;
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PhysicalMemoryAddress current_address = cs.base_address;
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const PhysicalMemoryAddress increment = cs.channel_control.address_step_reverse ? static_cast<u32>(-4) : UINT32_C(4);
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switch (cs.channel_control.sync_mode)
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{
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case SyncMode::Manual:
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{
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const u32 word_count = cs.block_control.manual.GetWordCount();
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Log_DebugPrintf("DMA%u: Copying %u words %s 0x%08X", static_cast<u32>(channel), word_count,
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copy_to_device ? "from" : "to", current_address);
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if (copy_to_device)
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TransferMemoryToDevice(channel, current_address, increment, word_count);
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else
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TransferDeviceToMemory(channel, current_address, increment, word_count);
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}
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break;
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case SyncMode::LinkedList:
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{
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if (!copy_to_device)
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{
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Panic("Linked list not implemented for DMA reads");
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}
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else
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{
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Log_DebugPrintf("DMA%u: Copying linked list starting at 0x%08X to device", static_cast<u32>(channel),
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current_address);
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for (;;)
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{
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u32 header;
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m_bus->DispatchAccess<MemoryAccessType::Read, MemoryAccessSize::Word>(current_address & ADDRESS_MASK, header);
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const u32 word_count = header >> 24;
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const u32 next_address = header & UINT32_C(0x00FFFFFF);
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Log_TracePrintf(" .. linked list entry at 0x%08X size=%u(%u words) next=0x%08X", current_address,
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word_count * UINT32_C(4), word_count, next_address);
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if (word_count > 0)
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TransferMemoryToDevice(channel, (current_address + sizeof(header)) & ADDRESS_MASK, 4, word_count);
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// Self-referencing DMA loops.. not sure how these are happening?
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if (current_address == next_address)
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{
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Log_ErrorPrintf("HACK: Aborting self-referencing DMA loop @ 0x%08X. Something went wrong to generate this.",
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current_address);
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break;
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}
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current_address = next_address;
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if (current_address & UINT32_C(0x800000))
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break;
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}
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}
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cs.base_address = current_address;
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}
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break;
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case SyncMode::Request:
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{
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Log_DebugPrintf("DMA%u: Copying %u blocks of size %u (%u total words) %s 0x%08X", static_cast<u32>(channel),
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cs.block_control.request.GetBlockCount(), cs.block_control.request.GetBlockSize(),
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cs.block_control.request.GetBlockCount() * cs.block_control.request.GetBlockSize(),
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copy_to_device ? "from" : "to", current_address);
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const u32 block_size = cs.block_control.request.GetBlockSize();
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u32 blocks_remaining = cs.block_control.request.block_count;
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if (copy_to_device)
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{
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do
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{
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blocks_remaining--;
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TransferMemoryToDevice(channel, current_address & ADDRESS_MASK, increment, block_size);
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current_address = (current_address + (increment * block_size));
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} while (cs.request && blocks_remaining > 0);
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}
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else
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{
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do
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{
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blocks_remaining--;
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TransferDeviceToMemory(channel, current_address & ADDRESS_MASK, increment, block_size);
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current_address = (current_address + (increment * block_size));
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} while (cs.request && blocks_remaining > 0);
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}
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cs.base_address = current_address & BASE_ADDRESS_MASK;
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cs.block_control.request.block_count = blocks_remaining;
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// finish transfer later if the request was cleared
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if (blocks_remaining > 0)
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return;
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}
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break;
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default:
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Panic("Unimplemented sync mode");
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break;
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}
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// start/busy bit is cleared on end of transfer
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cs.transfer_ticks = 0;
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cs.channel_control.enable_busy = false;
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if (m_DICR.IsIRQEnabled(channel))
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{
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Log_DebugPrintf("Set DMA interrupt for channel %u", static_cast<u32>(channel));
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m_DICR.SetIRQFlag(channel);
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UpdateIRQ();
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}
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}
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void DMA::TransferMemoryToDevice(Channel channel, u32 address, u32 increment, u32 word_count)
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{
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// Read from memory. Wrap-around?
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if (m_transfer_buffer.size() < word_count)
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m_transfer_buffer.resize(word_count);
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if (increment > 0 && ((address + (increment * word_count)) & ADDRESS_MASK) > address)
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{
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m_bus->ReadWords(address, m_transfer_buffer.data(), word_count);
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}
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else
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{
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for (u32 i = 0; i < word_count; i++)
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{
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m_bus->DispatchAccess<MemoryAccessType::Read, MemoryAccessSize::Word>(address, m_transfer_buffer[i]);
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address = (address + increment) & ADDRESS_MASK;
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}
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}
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switch (channel)
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{
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case Channel::GPU:
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m_gpu->DMAWrite(m_transfer_buffer.data(), word_count);
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break;
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case Channel::SPU:
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m_spu->DMAWrite(m_transfer_buffer.data(), word_count);
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break;
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case Channel::MDECin:
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m_mdec->DMAWrite(m_transfer_buffer.data(), word_count);
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break;
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case Channel::CDROM:
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case Channel::MDECout:
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case Channel::PIO:
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default:
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Panic("Unhandled DMA channel for device write");
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break;
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}
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}
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void DMA::TransferDeviceToMemory(Channel channel, u32 address, u32 increment, u32 word_count)
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{
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if (m_transfer_buffer.size() < word_count)
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m_transfer_buffer.resize(word_count);
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// Read from device.
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switch (channel)
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{
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case Channel::OTC:
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{
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// clear ordering table
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// this always goes in reverse, so we can generate values in reverse order and write it forwards
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if (((address - (4 * word_count)) & ADDRESS_MASK) < address)
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{
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const u32 end_address = (address - (4 * (word_count - 1))) & ADDRESS_MASK;
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u32 value = end_address;
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m_transfer_buffer[0] = UINT32_C(0xFFFFFF);
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for (u32 i = 1; i < word_count; i++)
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{
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m_transfer_buffer[i] = value;
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value = (value + 4) & ADDRESS_MASK;
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}
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m_bus->WriteWords(end_address, m_transfer_buffer.data(), word_count);
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}
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else
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{
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for (u32 i = 0; i < word_count; i++)
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{
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u32 value = (i == word_count - 1) ? UINT32_C(0xFFFFFFF) : ((address - 4) & ADDRESS_MASK);
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m_bus->DispatchAccess<MemoryAccessType::Write, MemoryAccessSize::Word>(address, value);
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address = (address - 4) & ADDRESS_MASK;
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}
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}
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return;
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}
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break;
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case Channel::GPU:
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m_gpu->DMARead(m_transfer_buffer.data(), word_count);
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break;
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case Channel::CDROM:
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m_cdrom->DMARead(m_transfer_buffer.data(), word_count);
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break;
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case Channel::SPU:
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m_spu->DMARead(m_transfer_buffer.data(), word_count);
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break;
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case Channel::MDECout:
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m_mdec->DMARead(m_transfer_buffer.data(), word_count);
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break;
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case Channel::MDECin:
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case Channel::PIO:
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default:
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Panic("Unhandled DMA channel for device read");
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std::fill_n(m_transfer_buffer.begin(), word_count, UINT32_C(0xFFFFFFFF));
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break;
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}
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if (increment > 0 && ((address + (increment * word_count)) & ADDRESS_MASK) > address)
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|
{
|
|
m_bus->WriteWords(address, m_transfer_buffer.data(), word_count);
|
|
}
|
|
else
|
|
{
|
|
for (u32 i = 0; i < word_count; i++)
|
|
{
|
|
m_bus->DispatchAccess<MemoryAccessType::Write, MemoryAccessSize::Word>(address, m_transfer_buffer[i]);
|
|
address = (address + increment) & ADDRESS_MASK;
|
|
}
|
|
}
|
|
}
|