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134 lines
7.0 KiB
C
134 lines
7.0 KiB
C
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switch (uarch) {
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case cpuinfo_uarch_cortex_a5:
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/*
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* Cortex-A5 Technical Reference Manual:
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* 6.3.1. Micro TLB
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* The first level of caching for the page table information is a micro TLB of
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* 10 entries that is implemented on each of the instruction and data sides.
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* 6.3.2. Main TLB
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* Misses from the instruction and data micro TLBs are handled by a unified main TLB.
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* The main TLB is 128-entry two-way set-associative.
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*/
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break;
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case cpuinfo_uarch_cortex_a7:
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/*
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* Cortex-A7 MPCore Technical Reference Manual:
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* 5.3.1. Micro TLB
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* The first level of caching for the page table information is a micro TLB of
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* 10 entries that is implemented on each of the instruction and data sides.
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* 5.3.2. Main TLB
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* Misses from the micro TLBs are handled by a unified main TLB. This is a 256-entry 2-way
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* set-associative structure. The main TLB supports all the VMSAv7 page sizes of
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* 4KB, 64KB, 1MB and 16MB in addition to the LPAE page sizes of 2MB and 1G.
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*/
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break;
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case cpuinfo_uarch_cortex_a8:
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/*
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* Cortex-A8 Technical Reference Manual:
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* 6.1. About the MMU
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* The MMU features include the following:
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* - separate, fully-associative, 32-entry data and instruction TLBs
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* - TLB entries that support 4KB, 64KB, 1MB, and 16MB pages
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*/
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break;
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case cpuinfo_uarch_cortex_a9:
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/*
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* ARM Cortex‑A9 Technical Reference Manual:
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* 6.2.1 Micro TLB
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* The first level of caching for the page table information is a micro TLB of 32 entries on the data side,
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* and configurable 32 or 64 entries on the instruction side.
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* 6.2.2 Main TLB
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* The main TLB is implemented as a combination of:
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* - A fully-associative, lockable array of four elements.
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* - A 2-way associative structure of 2x32, 2x64, 2x128 or 2x256 entries.
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*/
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break;
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case cpuinfo_uarch_cortex_a15:
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/*
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* ARM Cortex-A15 MPCore Processor Technical Reference Manual:
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* 5.2.1. L1 instruction TLB
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* The L1 instruction TLB is a 32-entry fully-associative structure. This TLB caches entries at the 4KB
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* granularity of Virtual Address (VA) to Physical Address (PA) mapping only. If the page tables map the
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* memory region to a larger granularity than 4K, it only allocates one mapping for the particular 4K region
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* to which the current access corresponds.
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* 5.2.2. L1 data TLB
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* There are two separate 32-entry fully-associative TLBs that are used for data loads and stores,
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* respectively. Similar to the L1 instruction TLB, both of these cache entries at the 4KB granularity of
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* VA to PA mappings only. At implementation time, the Cortex-A15 MPCore processor can be configured with
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* the -l1tlb_1m option, to have the L1 data TLB cache entries at both the 4KB and 1MB granularity.
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* With this configuration, any translation that results in a 1MB or larger page is cached in the L1 data
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* TLB as a 1MB entry. Any translation that results in a page smaller than 1MB is cached in the L1 data TLB
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* as a 4KB entry. By default, all translations are cached in the L1 data TLB as a 4KB entry.
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* 5.2.3. L2 TLB
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* Misses from the L1 instruction and data TLBs are handled by a unified L2 TLB. This is a 512-entry 4-way
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* set-associative structure. The L2 TLB supports all the VMSAv7 page sizes of 4K, 64K, 1MB and 16MB in
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* addition to the LPAE page sizes of 2MB and 1GB.
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*/
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break;
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case cpuinfo_uarch_cortex_a17:
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/*
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* ARM Cortex-A17 MPCore Processor Technical Reference Manual:
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* 5.2.1. Instruction micro TLB
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* The instruction micro TLB is implemented as a 32, 48 or 64 entry, fully-associative structure. This TLB
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* caches entries at the 4KB and 1MB granularity of Virtual Address (VA) to Physical Address (PA) mapping
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* only. If the translation tables map the memory region to a larger granularity than 4KB or 1MB, it only
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* allocates one mapping for the particular 4KB region to which the current access corresponds.
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* 5.2.2. Data micro TLB
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* The data micro TLB is a 32 entry fully-associative TLB that is used for data loads and stores. The cache
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* entries have a 4KB and 1MB granularity of VA to PA mappings only.
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* 5.2.3. Unified main TLB
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* Misses from the instruction and data micro TLBs are handled by a unified main TLB. This is a 1024 entry
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* 4-way set-associative structure. The main TLB supports all the VMSAv7 page sizes of 4K, 64K, 1MB and 16MB
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* in addition to the LPAE page sizes of 2MB and 1GB.
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*/
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break;
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case cpuinfo_uarch_cortex_a35:
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/*
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* ARM Cortex‑A35 Processor Technical Reference Manual:
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* A6.2 TLB Organization
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* Micro TLB
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* The first level of caching for the translation table information is a micro TLB of ten entries that
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* is implemented on each of the instruction and data sides.
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* Main TLB
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* A unified main TLB handles misses from the micro TLBs. It has a 512-entry, 2-way, set-associative
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* structure and supports all VMSAv8 block sizes, except 1GB. If it fetches a 1GB block, the TLB splits
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* it into 512MB blocks and stores the appropriate block for the lookup.
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*/
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break;
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case cpuinfo_uarch_cortex_a53:
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/*
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* ARM Cortex-A53 MPCore Processor Technical Reference Manual:
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* 5.2.1. Micro TLB
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* The first level of caching for the translation table information is a micro TLB of ten entries that is
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* implemented on each of the instruction and data sides.
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* 5.2.2. Main TLB
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* A unified main TLB handles misses from the micro TLBs. This is a 512-entry, 4-way, set-associative
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* structure. The main TLB supports all VMSAv8 block sizes, except 1GB. If a 1GB block is fetched, it is
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* split into 512MB blocks and the appropriate block for the lookup stored.
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*/
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break;
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case cpuinfo_uarch_cortex_a57:
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/*
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* ARM® Cortex-A57 MPCore Processor Technical Reference Manual:
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* 5.2.1 L1 instruction TLB
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* The L1 instruction TLB is a 48-entry fully-associative structure. This TLB caches entries of three
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* different page sizes, natively 4KB, 64KB, and 1MB, of VA to PA mappings. If the page tables map the memory
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* region to a larger granularity than 1MB, it only allocates one mapping for the particular 1MB region to
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* which the current access corresponds.
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* 5.2.2 L1 data TLB
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* The L1 data TLB is a 32-entry fully-associative TLB that is used for data loads and stores. This TLB
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* caches entries of three different page sizes, natively 4KB, 64KB, and 1MB, of VA to PA mappings.
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* 5.2.3 L2 TLB
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* Misses from the L1 instruction and data TLBs are handled by a unified L2 TLB. This is a 1024-entry 4-way
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* set-associative structure. The L2 TLB supports the page sizes of 4K, 64K, 1MB and 16MB. It also supports
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* page sizes of 2MB and 1GB for the long descriptor format translation in AArch32 state and in AArch64 state
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* when using the 4KB translation granule. In addition, the L2 TLB supports the 512MB page map size defined
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* for the AArch64 translations that use a 64KB translation granule.
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*/
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break;
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}
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